1. Mousumi Dhar
Member

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1. Ankit Das
Member

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Member

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1. Lorin Ahmed
Member

A partial Order <= is defined on the set S={x, a1, a2, a3,…, an, y} as x<=ai and ai<=y. for all i, where n >=1. The number of totaL orders on the set S which contains the partial order <= is:
(A) n!
(B) n+2
(C) n
(D) 1

I think the answer is B.

Does anybody else know the answer…

1. Nayaan Dixit
Member

what is the Exact difference b/w superkey,primary key and Candiate key,,,,

1. Lorin Ahmed
Member

Super key is super set of attributes forming a key, primary key is the exact set of attributes which serve the purpose of identifying any tuple in a relation while a candidate key is any set of attributes which has the unique property, and they can be a primary key. Basically a primary key is also first a candidate key, there can be several candidate keys in a relation, among which one primary key can be choosen to identify the tuples in the relation… while taking super set of any of the candidate key makes it a super key.

1. @ Lorin Ahmed:
According to me the answer should be c.
Totally ordered set (TOS) is one in which there exists an ordering among every pair of elements. So the TOS for the problem are: (x,a1,y) (x,a2,y) (x,a3,y)….(x,an,y). Any set involving more than one ‘a’ cannot be totally ordered because no ordering exists between the a’s. So total n TOS.

Q1. For inclusion to hold between two cache levels L1 and L2 in a multilevel cache hierarchy which of the following are necessary?
1. L1 must be write through cache
2. L2 must be write through cache
3. Associativity of L1 must be greater than that of L2
4. L2 cache must be atleast as large as L!

a. 1,2,3,4 b.1,2,4 c.1,4 d.4 only

Q2. For a disk with concentric circular tracks seek latency is not linearly proportional to seek distance due to
a. unfair arm scheduling proecss
b. higher capacity of tracks on the periphery of the platter
c. arm starting and stopping inertia
d. non-uniform distribution of request

Q3. DRAM has memory cycle time of 64 ns. it has to be refreshed 100 times per ns and each refresh takes 100ns. What percentage of memory cycle is used for refreshing?
a. 10 b.6.4 c.1 d.0.64

Q4. Refreshing rate of DRAM is in the range of
a. 3ms b.2ms c.50ms d.500ms

Thank you.

1. Lorin Ahmed
Member

Thanx Mahesh, I too thought that the answer of my question may be c as well, but what if i make TOS as (x,a1), (x, a2),…..(x,an),(a1, y)…(an,y) apart from the TOS of 3 elements. Then there should be total 3n possible TOS. what say???

1. Lorin Ahmed
Member

The answer to your first question is D. Since inclusion property says that the higher levels of memory should have all the data of all the lower levels. Its doesnt talk about the consistency of the data. Thus, for all the data to be present in the higher level of cache, the higher level should be atleast as big as the lower level.

1. Lorin Ahmed
Member

And i think there is some mistyping in the line of ques 3 “there are 100 refreshes per 1 ns and eash refresh takes 100 ns”, due to which m unable to understand the question. And since ques 4 is linked to ques 3, i wont be able to try that as well.

1. Lorin Ahmed
Member

global int i=100, j=5;
void P(x){
int i=10;
print(x+10);
i=200;
j=20;
print(x);
}
main(){
P(i+j);
}

If the programming language uses dynamic scoping and call by name parameter passing mechanism, the values printed by the above program are
(A) 115, 220
(B) 25,220
(C) 25,15
(D) 115,105

1. Lorin Ahmed
Member

I think the answer is B.

1. The minimum number of comparisons required to determine if an integer appears more than n/2 times in sorted array of n integers is:
(a) n
(b) log n
(c) log * n
(d) 1 (constant)??????

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