On-Chip Communication Architectures E&TC 8th Sem Syllabus for BE 2017 Regulation Anna Univ (Professional Elective IV) detail syllabus for Electronics & Communication Engineering (E&Tc), 2017 regulation is collected from the Anna Univ official website and presented for students of Anna University. The details of the course are: course code (TL8012), Category (PE), Contact Periods/week (3), Teaching hours/week (3), Practical Hours/week (0). The total course credits are given in combined syllabus.
For all other e&tc 8th sem syllabus for be 2017 regulation anna univ you can visit E&TC 8th Sem syllabus for BE 2017 regulation Anna Univ Subjects. For all other Professional Elective IV subjects do refer to Professional Elective IV. The detail syllabus for on-chip communication architectures is as follows.
Course Objective:
- To understand the basic concepts of bus-based communication architectures and standards
- Provide an understanding of the concepts and building blocks of System-on-Chip (SoC) design
- To understand the concepts and building blocks of Network-on-Chip (NoC) design
- Provide an understanding of emerging on-chip interconnect technologies
Unit I
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Unit II
On-Chip Communication Architecture Standards
Standard On-Chip Bus-Based Communication Architectures: AMBA 2.0, AMBA3.0, IBM CoreConnect, STMicroelectronics STBus, Sonics SMART Interconnect, OpenCores Wishbone, Altera Avalon, Socket-Based On-Chip Bus Interface Standards: Open Core Protocol.
Unit III
System On Chip
System design methodologies: System on Board (SoB) – System on Chip (SoC) – Generic SoC Architecture Components: Generic SoC Block Diagram – Subsystems of an SoC – Platform-Based SoC Design: Concept of the Platform, Types of Platforms: Processor-Centric Platform, Application-Specific Platform ,Fully Programmable Platform, Communication-Centric Platform.
Unit IV
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Unit V
Emerging On-Chip Interconnect Technologies
Optical Interconnects (OIs) -Use of OIs for On-Chip Communication – RF/Wireless Interconnects
– Use of RF/Wireless Interconnects for On-Chip Communication – Carbon Nanotube (CNT) Interconnects – Circuit Parameters for Isolated Single-Walled Carbon Nanotubes (SWCNTS) -Circuit Parameters for a Bundle of SWCNTs – Comparison between Copper and SWCNT-Bundles
– Using CNTs for On-Chip Communication.
Course Outcome:
Upon completion of the course, the student would be able to:
- Know the various bus-based communication architectures and standards
- Know the concepts and building blocks of System-on-Chip (SoC) and Network on Chip (NoC)
- Know the emerging on-chip interconnect technologies
Text Books:
- SudeepPasricha, NikilDutt On-Chip Communication Architectures: System on Chip Interconnect Morgan Kaufmann Publishers Inc, 2008. (For unit-1&2)
- Mishra, Sanjeeb; Rousseau, Vijayakrishnan; Singh, Neeraj Kumar System on Chip Interfaces for Low Power Design, Morgan Kaufmann, 2015. (For unit-3,4&5)
References:
- Hoi-Jun Yoo, Kangmin Lee, Jun Kyong Kim, Low-Power NoC for High Performance SoC Design, CRC Press, 2008.
- Michael J. Flynn, Wayne Luk Computer System Design: System-on-Chip Wiley-Blackwell, 2011.
For detail syllabus of all other subjects of BE E&Tc, 2017 regulation do visit E&Tc 8th Sem syllabus for 2017 Regulation.
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