Low Power Soc Design Ece 8th Sem Syllabus for BE 2017 Regulation Anna Univ (Professional Elective IV) detail syllabus for Electronics And Communication Engineering (Ece), 2017 regulation is collected from the Anna Univ official website and presented for students of Anna University. The details of the course are: course code (EC8007), Category (PE), Contact Periods/week (3), Teaching hours/week (3), Practical Hours/week (0). The total course credits are given in combined syllabus.
For all other ece 8th sem syllabus for be 2017 regulation anna univ you can visit Ece 8th Sem syllabus for BE 2017 regulation Anna Univ Subjects. For all other Professional Elective IV subjects do refer to Professional Elective IV. The detail syllabus for low power soc design is as follows.
Course Objective:
The student should be made to:
- Identify sources of power in an IC.
- Understand basic principle of System on Chip design
- Learn optimization of power in combinational and sequential logic machines for SoC Design
- Identify suitable techniques to reduce the power dissipation and design circuits with low power dissipation.
Unit I
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Unit II
System-On-Chip Design
System-on-Chip Concept, Design Principles in SoC Architecture, SoC Design Flow, Platformbased and IP based SoC Designs, Basic Concepts of Bus-Based Communication Architectures. High performance algorithms for ASICs/ SoCs as case studies – Canonic Signed Digit Arithmetic, KCM, Distributed Arithmetic, High performance digital filters for sigma-delta ADC
Unit III
Power Optimization of Combinational and Sequential Logic Machines for Soc
Introduction to Standard Cell-Based Layout – Simulation – Combinational Network Delay – Logic and interconnect Design – Power Optimization – Switch Logic Networks. Introduction – Latches and Flip-Flops – Sequential Systems and Clocking Disciplines – Sequential System Design – Power Optimization – Design Validation – Sequential Testing.
Unit IV
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Unit V
Floor Planning
Floor-planning Methods – Block Placement and Channel Definition – Global Routing – switchbox Routing – Power Distribution – Clock Distributions – Floor-planning Tips – Design Validation – Off-Chip Connections – Packages, The I/O Architecture – PAD Design
Course Outcome:
At the end of the course, the student should be able to:
- Analyze and design low-power VLSI circuits using different circuit technologies for system on chip design
Text Books:
- J.Rabaey, Low Power Design Essentials (Integrated Circuits and Systems), Springer, 2009
- Wayne Wolf, Modern VLSI Design – System – on – Chip Design, Prentice Hall, 3rd Edition, 2008.
References:
- J.B.Kuo and J.H.Lou, Low-voltage CMOS VLSI Circuits, Wiley, 1999.
- A.Bellaowar and M.I.Elmasry,Low power Digital VLSI Design, Circuits and Systems, Kluwer, 1996.
- Wayne Wolf, Modern VLSI Design – IP based Design, Prentice Hall, 4th Edition, 2008.
- M.J.S. Smith : Application Specific Integrated Circuits, Pearson, 2003
- Sudeep Pasricha and NikilDutt, On-Chip Communication Architectures System on Chip Interconnect, Elsevier, 2008
- Recent literature in Low Power VLSI Circuits.
- Recent literature in Design of ASICs
For detail syllabus of all other subjects of BE Ece, 2017 regulation do visit Ece 8th Sem syllabus for 2017 Regulation.
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