VLSI Design Laboratory detail syllabus for Electronics & Communication Engineering (E&Tc), 2017 regulation is taken from Anna University official website and presented for students of Anna University. The details of the course are: course code (EC8661), Category (PC), Contact Periods/week (4), Teaching hours/week (0), Practical Hours/week (0). The total course credits are 4.
For all other e&tc 6th sem syllabus for be 2017 regulation anna univ you can visit E&TC 6th Sem syllabus for BE 2017 regulation Anna Univ Subjects. The detail syllabus for vlsi design laboratory is as follows.”
Course Objective:
The student should be made:
- To learn Hardware Descriptive Language(Verilog/VHDL)
- To learn the fundamental principles of VLSI circuit design in digital and analog domain
- To familiarize fusing of logical modules on FPGAs
- To provide hands on design experience with professional design (EDA) platforms
Part I Experiments:
Digital System Design Using Hdl and Fpga (24 Periods)
- Design an Adder (Min 8 Bit) using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA
- Design a Multiplier (4 Bit Min) using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA
- Design an ALU using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA
- Design a Universal Shift Register using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA
- Design Finite State Machine (Moore/Mealy) using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA
- Design Memories using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA
- Compare pre synthesis and post synthesis simulation for experiments 1 to 6.
- Requirements: Xilinx ISE/Altera Quartus/ equivalent EDA Tools along with Xilinx/Altera/equivalent FPGA Boards
Part II Experiments:
Digital Circuit Design (24 Periods)
- Design and simulate a CMOS inverter using digital flow
- Design and simulate a CMOS Basic Gates and Flip-Flops
- Design and simulate a 4-bit synchronous counter using a Flip-Flops
- Manual/Automatic Layout Generation and Post Layout Extraction for experiments 7 to 9
- Analyze the power, area and timing for experiments 7 to 9 by performing Pre Layout and Post Layout Simulations.
Part-III Experiments:
Analog Circuit Design (12 Periods)
- Design and Simulate a CMOS Inverting Amplifier.
- Design and Simulate basic Common Source, Common Gate and Common Drain Amplifiers.
- Analyze the input impedance, output impedance, gain and bandwidth for experiments 10 and 11 by performing Schematic Simulations.
- Design and simulate simple 5 transistor differential amplifier. Analyze Gain,
- Bandwidth and CMRR by performing Schematic Simulations.
Requirements: Cadence/Synopsis/ Mentor Graphics/Tanner/Equivalent Eda Tools
Course Outcome:
At the end of the course, the student should be able to:
- Write HDL code for basic as well as advanced digital integrated circuit
- Import the logic modules into FPGA Boards
- Synthesize Place and Route the digital IPs
- Design, Simulate and Extract the layouts of Digital and Analog IC Blocks using EDA tools
List of Equipment for a Batch of 30 Students
S.No Equipment Required
- Xilinx ISE/Altera Quartus/ equivalent EDA Tools 10 User License
- Xilinx/Altera/equivalent FPGA Boards 10 no
- Cadence/Synopsis/ Mentor Graphics/Tanner/equivalent EDA Tools 10 User License
- Personal Computer 30 no
For detail syllabus of all other subjects of BE E&Tc, 2017 regulation do visit E&Tc 6th Sem syllabus for 2017 Regulation.
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