Vlsi Design Laboratory Ece 6th Sem Syllabus for BE 2017 Regulation Anna Univ

Vlsi Design Laboratory detail syllabus for Electronics And Communication Engineering (Ece), 2017 regulation is taken from Anna University official website and presented for students of Anna University. The details of the course are: course code (EC8661), Category (PC), Contact Periods/week (4), Teaching hours/week (0), Practical Hours/week (0). The total course credits are 4.

For all other ece 6th sem syllabus for be 2017 regulation anna univ you can visit Ece 6th Sem syllabus for BE 2017 regulation Anna Univ Subjects. The detail syllabus for vlsi design laboratory is as follows.”

Course Objective:

The student should be made:

• To learn Hardware Descriptive Language(Verilog/VHDL)
• To learn the fundamental principles of VLSI circuit design in digital and analog domain
• To familiarize fusing of logical modules on FPGAs
• To provide hands on design experience with professional design (EDA) platforms

Experiments Part I:

Digital System Design using HDL and FPGA (24 Periods)

1. Design an Adder (Min 8 Bit) using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA
2. Design a Multiplier (4 Bit Min) using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA
3. Design an ALU using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA
4. Design a Universal Shift Register using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA
5. Design Finite State Machine (Moore/Mealy) using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA
6. Design Memories using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA

Compare pre synthesis and post synthesis simulation for experiments 1 to 6.

Requirements:
Xilinx ISE/Altera Quartus/ equivalent EDA Tools along with Xilinx/Altera/equivalent FPGA Boards

Experiments Part II:

Digital Circuit Design (24 Periods)

1. Design and simulate a CMOS inverter using digital flow
2. Design and simulate a CMOS Basic Gates and Flip-Flops
3. Design and simulate a 4-bit synchronous counter using a Flip-Flops

Manual/Automatic Layout Generation and Post Layout Extraction for experiments 7 to 9
Analyze the power, area and timing for experiments 7 to 9 by performing Pre Layout and Post Layout Simulations.

Experiments Part III:

Analog Circuit Design (12 Periods)

1. Design and Simulate a CMOS Inverting Amplifier.

Design and Simulate basic Common Source, Common Gate and Common Drain

2. Amplifiers.

Analyze the input impedance, output impedance, gain and bandwidth for experiments 10 and 11 by performing Schematic Simulations.
Design and simulate simple 5 transistor differential amplifier. Analyze Gain,

3. Bandwidth and CMRR by performing Schematic Simulations.

Requirements:
Cadence/Synopsis/ Mentor Graphics/Tanner/equivalent EDA Tools

Course Outcome:

At the end of the course, the student should be able to:

• Write HDL code for basic as well as advanced digital integrated circuit
• Import the logic modules into FPGA Boards
• Synthesize Place and Route the digital IPs
• Design, Simulate and Extract the layouts of Digital and Analog IC Blocks using EDA tools

List of Equipments for a Batch of 30 Students

S.NO EQUIPMENT REQUIRED

1. Xilinx ISE/Altera Quartus/ equivalent EDA Tools 10 User License
2. Xilinx/Altera/equivalent FPGA Boards 10 no
3. Cadence/Synopsis/ Mentor Graphics/Tanner/equivalent EDA Tools 10 User License
4. Personal Computer 30 no

For detail syllabus of all other subjects of BE Ece, 2017 regulation do visit Ece 6th Sem syllabus for 2017 Regulation.

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