EC5611: VLSI Laboratory Syllabus for ECE 6th Sem 2019 Regulation Anna University

VLSI Laboratory detailed syllabus for Electronics & Communication Engineering (ECE) for 2019 regulation curriculum has been taken from the Anna Universities official website and presented for the ECE students. For course code, course name, number of credits for a course and other scheme related information, do visit full semester subjects post given below.

For Electronics & Communication Engineering 6th Sem scheme and its subjects, do visit ECE 6th Sem 2019 regulation scheme. The detailed syllabus of vlsi laboratory is as follows.

Course Objective:

• To introduce the relevance of this course to the existing technology through demonstrations, case studies, simulations, contributions of scientist, national/international policies with a futuristic vision along with socio-economic impact and issues
• To learn the Hardware Description Language (Verilog/VHDL)
• To learn the fundamental principles of VLSI circuit design in digital and analog domain
• To familiarize fusing of logical modules on FPGAs
• To provide hands on design experience with hardware/software based embedded system.

Digital and Analog Experiments

I Digital Experiments – FPGA BASED EXPERIMENTS:

1. Design and simulation of Full adder and full subtractor
2. Design and simulation of multiplexer, Decoder and 4 bit comparator
3. Design and simulation of 8 bit adder
4. HDL based design entry and simulation of Ripple counter, synchronous counter and BCD counter
5. Design and simulation of simple state machines
6. 4 bit multiplier design and simulation using HDL
7. Synthesis, P&R and post P&R simulation of the components simulated in (1-6) above. Critical paths and static timing analysis results to be identified. Identify and verify possible conditions under which the blocks will fail to work correctly.
8. Hardware fusing and testing of each of the blocks simulated in (1-6). Use of either chipscope feature (Xilinx) or the signal tap feature (Altera) is a must. Invoke the PLL and demonstrate the use of the PLL module for clock generation in FPGAs..

II Analog / IC Design Experiments (Based on Cadence/Any other equivalent SPICE Circuit Simulator and FPAA based experiments)

1. Design and simulation of a simple five transistor differential amplifier – Measure gain, ICMR and CMRR
2. Layout generation, parasitic extraction and resimulation of the five transistor differential amplifier
3. Synthesis and standard cell based design of circuits simulated in 9 above. Identification of critical paths, power consumption
4. For experiment 11 above, P and R, Power and clock routing and post P and R simulation
5. Analysis of results of static timing analysis

FPAA Based Experiments:

1. Design, Simulate and implement an inverting gain amplifier, low pass, high pass filters and full wave rectifier. Analyze the frequency response of filters
2. Design and Implement a circuit which introduces noise tone to the audio and then bring the original audio by removing the noise tone

Course Outcome:

At the end of the course, the student should be able to

1. Ability to implement digital circuits in FPGA using HDL
2. Ability to realize digital circuits satisfying timing and area constraints
3. Ability to Synthesize, Place and Route the digital IPs
4. Ability to design, simulate and extract the layout of Analog IC Blocks using EDA tools
5. Ability to comprehend and appreciate the significance and role of this course in the present contemporary world

For detailed syllabus of all other subjects of Electronics & Communication Engineering, 2019 regulation curriculum do visit ECE 6th Sem subject syllabuses for 2019 regulation.

For all Electronics & Communication Engineering results, visit Anna University ECE all semester results direct link.