ECE

EC5023: CAD for VLSI Circuits Syllabus for ECE 8th Sem 2019 Regulation Anna University (Professional Elective-VI)

CAD for VLSI Circuits detailed syllabus for Electronics & Communication Engineering (ECE) for 2019 regulation curriculum has been taken from the Anna Universities official website and presented for the ECE students. For course code, course name, number of credits for a course and other scheme related information, do visit full semester subjects post given below.

For Electronics & Communication Engineering 8th Sem scheme and its subjects, do visit ECE 8th Sem 2019 regulation scheme. For Professional Elective-VI scheme and its subjects refer to ECE Professional Elective-VI syllabus scheme. The detailed syllabus of cad for vlsi circuits is as follows.

CAD for VLSI Circuits

Course Objective:

For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
Get it on Google Play.

Unit I

Vlsi Design Methodologies
Introduction to VLSI Design methodologies – Review of Data structures and algorithms – Review of VLSI Design automation tools – Algorithmic Graph Theory and Computational Complexity -Tractable and Intractable problems – general purpose methods for combinatorial optimization.

Unit II

For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
Get it on Google Play.

Unit III

Floor Planning
Floor planning concepts – shape functions and floor plan sizing – Types of local routing problems – Area routing – channel routing – global routing – algorithms for global routing.

Unit IV

For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
Get it on Google Play.

Unit V

Modelling and Synthesis
High level Synthesis – Hardware models – Internal representation – Allocation assignment and scheduling – Simple scheduling algorithm – Assignment problem – High level transformations.

Course Outcome:

For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
Get it on Google Play.

Text Books:

  1. S.H. Gerez, “Algorithms for VLSI Design Automation”, John Wiley and Sons,2002.

References:

  1. N.A. Sherwani, “Algorithms for VLSI Physical Design Automation”, Kluwer Academic Publishers,2002.

For detailed syllabus of all the other subjects of Electronics & Communication Engineering 8th Sem, visit ECE 8th Sem subject syllabuses for 2019 regulation.

For all Electronics & Communication Engineering results, visit Anna University ECE all semester results direct link.

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