3rd Sem, EIE

Digital Logic Circuits Eie 3rd Sem Syllabus for BE 2017 Regulation Anna Univ

Digital Logic Circuits detail syllabus for Electronics & Instrumentation Engineering (Eie), 2017 regulation is taken from Anna University official website and presented for students of Anna University. The details of the course are: course code (EE8351), Category (PC), Contact Periods/week (4), Teaching hours/week (2), Practical Hours/week (2). The total course credits are given in combined syllabus.

For all other eie 3rd sem syllabus for be 2017 regulation anna univ you can visit Eie 3rd Sem syllabus for BE 2017 regulation Anna Univ Subjects. The detail syllabus for digital logic circuits is as follows.”

Course Objective:

  • To study various number systems and simplify the logical expressions using Boolean functions
  • To study combinational circuits
  • To design various synchronous and asynchronous circuits.
  • To introduce asynchronous sequential circuits and PLDs
  • To introduce digital simulation for development of application oriented logic circuits.

Unit I

For complete syllabus and results, class timetable and more pls download iStudy. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.

Unit II

Combinational Circuits
Combinational logic – representation of logic functions-SOP and POS forms, K-map representations – minimization using K maps – simplification and implementation of combinational logic – multiplexers and de multiplexers – code converters, adders, subtractors, Encoders and Decoders.

Unit III

Synchronous Sequential Circuits
Sequential logic-SR, JK, D and T flip flops – level triggering and edge triggering – counters -asynchronous and synchronous type – Modulo counters – Shift registers – design of synchronous sequential circuits – Moore and Melay models- Counters, state diagram; state reduction; state assignment.

Unit IV

For complete syllabus and results, class timetable and more pls download iStudy. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.

Unit V

Vhdl
RTL Design – combinational logic – Sequential circuit – Operators – Introduction to Packages – Subprograms – Test bench. (Simulation /Tutorial Examples: adders, counters, flip flops, Multiplexers and De multiplexers).

Course Outcome:

  • Ability to design combinational and sequential Circuits.
  • Ability to simulate using software package.
  • Ability to study various number systems and simplify the logical expressions using Boolean functions
  • Ability to design various synchronous and asynchronous circuits.
  • Ability to introduce asynchronous sequential circuits and PLDs
  • Ability to introduce digital simulation for development of application oriented logic circuits.

Text Books:

  1. James W. Bignel, Digital Electronics, Cengage learning, 5th Edition, 2007.
  2. M. Morris Mano, Digital Design with an introduction to the VHDL, Pearson Education, 2013.
  3. Comer Digital Logic and State Machine Design, Oxford, 2012.

References:

  1. Mandal, Digital Electronics Principles and Application, McGraw Hill Edu, 2013.
  2. William Keitz, Digital Electronics-A Practical Approach with VHDL, Pearson, 2013.
  3. Thomas L.Floyd, Digital Fundamentals, 11th edition, Pearson Education, 2015.
  4. Charles H.Roth, Jr, Lizy Lizy Kurian John, Digital System Design using VHDL, Cengage, 2013.
  5. D.P.Kothari,J.S.Dhillon, Digital circuits and Design,Pearson Education, 2016.

For detail syllabus of all other subjects of BE Eie, 2017 regulation do visit Eie 3rd Sem syllabus for 2017 Regulation.

Dont forget to download iStudy for latest syllabus and results, class timetable and more.

Leave a Reply

Your email address will not be published. Required fields are marked *

*