5th Sem, ECE

Computer Architecture and Organization Ece 5th Sem Syllabus for BE 2017 Regulation Anna Univ

Computer Architecture and Organization detail syllabus for Electronics And Communication Engineering (Ece), 2017 regulation is taken from Anna University official website and presented for students of Anna University. The details of the course are: course code (EC8552), Category (PC), Contact Periods/week (3), Teaching hours/week (3), Practical Hours/week (0). The total course credits are given in combined syllabus.

For all other ece 5th sem syllabus for be 2017 regulation anna univ you can visit Ece 5th Sem syllabus for BE 2017 regulation Anna Univ Subjects. The detail syllabus for computer architecture and organization is as follows.”

Course Objective:

  • To make students understand the basic structure and operation of digital computer
  • To familiarize with implementation of fixed point and floating-point arithmetic operations
  • To study the design of data path unit and control unit for processor
  • To understand the concept of various memories and interfacing
  • To introduce the parallel processing technique

Unit I

For complete syllabus and results, class timetable and more pls download iStudy. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.

Unit II

Arithmetic
Fixed point Addition, Subtraction, Multiplication and Division. Floating Point arithmetic, High performance arithmetic, Subword parallelism

Unit III

the Processor
Introduction, Logic Design Conventions, Building a Datapath – A Simple Implementation scheme -An Overview of Pipelining – Pipelined Datapath and Control. Data Hazards: Forwarding versus Stalling, Control Hazards, Exceptions, Parallelism via Instructions.

Unit IV

For complete syllabus and results, class timetable and more pls download iStudy. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.

Unit V

Advanced Computer Architecture
Parallel processing architectures and challenges, Hardware multithreading, Multicore and shared memory multiprocessors, Introduction to Graphics Processing Units, Clusters and Warehouse scale computers – Introduction to Multiprocessor network topologies.

Course Outcome:

At the end of the course, the student should be able to

  • Describe data representation, instruction formats and the operation of a digital computer
  • Illustrate the fixed point and floating-point arithmetic for ALU operation
  • Discuss about implementation schemes of control unit and pipeline performance
  • Explain the concept of various memories, interfacing and organization of multiple processors
  • Discuss parallel processing technique and unconventional architectures

Text Books:

  1. David A. Patterson and John L. Hennessey, Computer Organization and Design, Fifth edition, Morgan Kauffman / Elsevier, 2014. (Unit I-V)
  2. Miles J. Murdocca and Vincent P. Heuring, Computer Architecture and Organization: An Integrated approach, Second edition, Wiley India Pvt Ltd, 2015 (Unit IV,V)

References:

  1. V. Carl Hamacher, Zvonko G. Varanesic and Safat G. Zaky, Computer Organization, Fifth edition, Mc Graw-Hill Education India Pvt Ltd, 2014.
  2. William Stallings Computer Organization and Architecture, Seventh Edition, Pearson Education, 2006.
  3. Govindarajalu, Computer Architecture and Organization, Design Principles and Applications”, Second edition, McGraw-Hill Education India Pvt Ltd, 2014.

For detail syllabus of all other subjects of BE Ece, 2017 regulation do visit Ece 5th Sem syllabus for 2017 Regulation.

Dont forget to download iStudy for latest syllabus and results, class timetable and more.

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