CEC370: Low Power IC Design syllabus for ETE 2021 regulation (Professional Elective-I)

Low Power IC Design detailed syllabus for Electronics & Telecommunication Engineering (ETE) for 2021 regulation curriculum has been taken from the Anna Universities official website and presented for the ETE students. For course code, course name, number of credits for a course and other scheme related information, do visit full semester subjects post given below.

For Electronics & Telecommunication Engineering 5th Sem scheme and its subjects, do visit ETE 5th Sem 2021 regulation scheme. For Professional Elective-I scheme and its subjects refer to ETE Professional Elective-I syllabus scheme. The detailed syllabus of low power ic design is as follows.

Course Objectives:

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Unit I

FUNDAMENTALS OF LOW POWER CIRCUITS
Need for Low Power Circuit Design, Sources of Power Dissipation – Switching Power Dissipation, Short Circuit Power Dissipation, Leakage Power Dissipation, Glitching Power Dissipation, Short Channel Effects -Drain Induced Barrier Lowering and Punch Through, Surface Scattering, Velocity Saturation, Impact Ionization, Hot Electron Effect.

Unit II

LOW-POWER DESIGN APPROACHES
Low-Power Design through Voltage Scaling: VTCMOS circuits, MTCMOS circuits, Architectural Level Approach -Pipelining and Parallel Processing Approaches. Switched Capacitance Minimization Approaches: System Level Measures, Circuit Level Measures, Mask level Measures.

Unit III

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Unit IV

LOW-VOLTAGE LOW-POWER MULTIPLIERS
Introduction, Overview of Multiplication, Types of Multiplier Architectures, Braun Multiplier, Baugh-Wooley Multiplier, Booth Multiplier, Introduction to Wallace Tree Multiplier

Unit V

LOW-VOLTAGE LOW-POWER MEMORIES
Basics of ROM, Low-Power ROM Technology, Future Trend and Development of ROMs, Basics of SRAM, Memory Cell, Precharge and Equalization Circuit, LowPower SRAM Technologies, Basics of DRAM, Self-Refres Circuit, Future Trend and Development of DRAM.

Practical Exercises

1. Modeling and sources of power consumption
2. Power estimation at different design levels (mainly circuit, transistor, and gate)
3. Power optimization for combinational circuits
4. Power optimization for sequential circuits
5. Power optimization for RT and algorithmic levels.

Course Outcomes:

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Text Books:

1. Sung-Mo Kang, Yusuf Leblebici, “CMOS Digital Integrated Circuits – Analysis and Design”, TMH, 2011.
2. Kiat-Seng Yeo, Kaushik Roy, “Low-Voltage, Low-Power VLSI Subsystems”, TMH Professional Engineering, 2004.

Reference Books:

1. Ming-BO Lin, “Introduction to VLSI Systems: A Logic, Circuit and System Perspective”, CRC Press, 2012.
2. Anantha Chandrakasan, “Low Power CMOS Design”, IEEE Press, /Wiley International, 1998
3. Kaushik Roy, Sharat C. Prasad, “Low Power CMOS VLSI Circuit Design”, John Wiley, & Sons, 2000.
4. Gary K. Yeap, “Practical Low Power Digital VLSI Design”, Kluwer Academic Press, 2002
5. Bellamour, M. I. Elamasri, “Low Power CMOS VLSI Circuit Design”, A Kluwer Academic Press, 1995.
6. Siva G. Narendran, Anatha Chandrakasan, “Leakage in Nanometer CMOS Technologies”, Springer, 2005

For detailed syllabus of all the other subjects of Electronics & Telecommunication Engineering 5th Sem, visit ETE 5th Sem subject syllabuses for 2021 regulation.

For all Electronics & Telecommunication Engineering results, visit Anna University ETE all semester results direct link.