VLSI Testing and Design For Testability detailed syllabus for Electronics & Telecommunication Engineering (ETE) for 2021 regulation curriculum has been taken from the Anna Universities official website and presented for the ETE students. For course code, course name, number of credits for a course and other scheme related information, do visit full semester subjects post given below.
For Electronics & Telecommunication Engineering 5th Sem scheme and its subjects, do visit ETE 5th Sem 2021 regulation scheme. For Professional Elective-I scheme and its subjects refer to ETE Professional Elective-I syllabus scheme. The detailed syllabus of vlsi testing and design for testability is as follows.
Course Objectives:
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Unit I
TEST REQUIREMENTS AND METRICS
Validation platforms- SOC design methodology, IP components, Integration, Clocking, I/Os and interfaces, Device modes, Logic, memories, analog, I/Os, power management; Test requirements-Test handoffs, Testers Where DUT and DFT fit into design / framework; Test- ATPG, DFT, BIST, COF, TTR; Test cost metrics and test economics; Logic fault models- SAF, TDF, PDF, Iddq, St-BDG, Dy-BDG, SDD; Basics of test generation and fault simulation- Combinational circuits, Sequential; Specific algorithmic approaches, CAD framework, Optimisations.
Unit II
SCAN DESIGN AND BIST
Scan Design- Scan design requirements, Types of scan and control mechanisms, Test pattern construction for scan, Managing scan in IPs and SOCs, Scan design optimisations, Partitioning, Clocking requirements for scan and delay fault testing, Speed of operation; BIST – Framework, Controller configurations, FSMs, LFSRs, STUMPS architecture, Scan compression and bounds, Test per cycle, Test per scan, Self-testing and self-checking circuits, Online test.
Unit III
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Unit IV
DESIGN CONSIDERATIONS AND POWER MANAGEMENT DURING TEST
Design Considerations- Design considerations, Physical design congestion, Partitioning, Clocks, Test modes, Pins, Test scheduling, Embedded test, Architecture improvements, Test in the presence of security; Power management during test- Methods for low power test, ATPG methods, DFT methods, Scan methods, Low power compression, Test of power management, Implications of power excursions, Optimisations.
Unit V
ANALOG TEST
Test requirements. DFT methods. BIST methods. Test versus measurement. Defect tests versus performance tests. Tests for specific modules – PLL, I/Os, ADC, DAC, SerDes, etc. RF test requirements.
Course Outcomes:
At the end of this course, the students will be able to:
- Understand logic and fault simulation requirements and testability measures.
- Understand the Design for Testability.
- Develop interfacing and memory testing.
- Perform testing with power management techniques.
- :Carry-out fault Detection in analog circuits.
Text Books:
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For detailed syllabus of all the other subjects of Electronics & Telecommunication Engineering 5th Sem, visit ETE 5th Sem subject syllabuses for 2021 regulation.
For all Electronics & Telecommunication Engineering results, visit Anna University ETE all semester results direct link.