VLSI Testing and Design For Testability detailed syllabus for Electronics & Communication Engineering (ECE) for 2021 regulation curriculum has been taken from the Anna Universities official website and presented for the ECE students. For course code, course name, number of credits for a course and other scheme related information, do visit full semester subjects post given below.
For Electronics & Communication Engineering 5th Sem scheme and its subjects, do visit ECE 5th Sem 2021 regulation scheme. For Professional Elective-I scheme and its subjects refer to ECE Professional Elective-I syllabus scheme. The detailed syllabus of vlsi testing and design for testability is as follows.
Course Objectives:
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Unit I
TEST REQUIREMENTS AND METRICS 9 Validation platforms- SOC design methodology, IP components, Integration, Clocking, I/Os and interfaces, Device modes, Logic, memories, analog, I/Os, power management; Test requirements-Test handoffs, Testers Where DUT and DFT fit into design / framework; Test- ATPG, DFT, BIST, COF, TTR; Test cost metrics and test economics; Logic fault models- SAF, TDF, PDF, Iddq, St-BDG, Dy-BDG, SDD; Basics of test generation and fault simulation- Combinational circuits, Sequential; Specific algorithmic approaches, CAD framework, Optimisations.
Unit II
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Unit III
MEMORY TEST AND TEST INTERFACES 9 Memory Test -Memory fault models, Functional architecture as applicable to test, Test of memories, Test of logic around memories, BIST controller configuration, Test of logic around memories, DFT and architecture enhancements, Algorithmic optimisations; Test Interfaces-Test control requirements, Test interfaces – 1500, JTAG, Hierarchical, serial control, Module / IP test, SOC test, Board test, System test, Boundary scan.
Unit IV
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Unit V
ANALOG TEST 9 Test requirements. DFT methods. BIST methods. Test versus measurement. Defect tests versus performance tests. Tests for specific modules – PLL, I/Os, ADC, DAC, SerDes, etc. RF test requirements.
Course Outcomes:
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Text Books:
- Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits,Vishwani Agrawal and Michael Bushnell, Springer, 2002.
For detailed syllabus of all the other subjects of Electronics & Communication Engineering 5th Sem, visit ECE 5th Sem subject syllabuses for 2021 regulation.
For all Electronics & Communication Engineering results, visit Anna University ECE all semester results direct link.