Validation and Testing Technology detailed syllabus for Electronics & Telecommunication Engineering (ETE) for 2021 regulation curriculum has been taken from the Anna Universities official website and presented for the ETE students. For course code, course name, number of credits for a course and other scheme related information, do visit full semester subjects post given below.
For Electronics & Telecommunication Engineering 5th Sem scheme and its subjects, do visit ETE 5th Sem 2021 regulation scheme. For Professional Elective-I scheme and its subjects refer to ETE Professional Elective-I syllabus scheme. The detailed syllabus of validation and testing technology is as follows.
Course Objectives:
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Unit I
TECHNOLOGY INTRODUCTION:
Introduction to IC Technology – MOS, PMOS, NMOS, CMOS & BiCMOS Technologies. VLSI Fabrication, Oxidation, Lithography, Diffusion, Ion Implantation, Metallization, Integrated Resistors and Capacitors.
Unit II
MOS THEORY ANALYSIS-I
Basic Electrical Properties of MOS Circuits: Ids-Vds Relationships, MOS Transistor Threshold Voltage Vth, gm, gds, Figure of Merit wo, Short Channel and Narrow Channel Width Effects.
Unit III
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Unit IV
CMOS CIRCUIT CHARACTERISATION AND PERFORMANCE ESTIMATION 6
Sheet Resistance RS, conductivity and its Concept to MOS, Area Capacitance Units, Calculations -Delays, Driving Large Capacitive Loads, Delay Estimation, Logical Effort and Transistor Sizing, Power Dissipation, Reliability.
Unit V
BASIC OF SILICON VALIDATION
Need for Testing, Testing at Various Levels, Objectives of Testing – VLSI Test process and Test Equipment – Types of Testing: Functionality Tests, Silicon Debug, Manufacturing Tests, Defect during manufacturing – Fault Modelling, Observability and Controllability, Fault Coverage, Fault Sampling – ATE, Test economics.
Practical Exercises
- MOS TESTING for Ids-Vds Relationships
- MOSFET testing for threshold voltage like Vth, gate breakdown voltage.
- Sheet resistivity measurement.
- Conductivity measurement.
- Inverter testing
- Designing of CMOS inverter/ logic gate and testing of delay estimation.
List of equipment needed
- Dual channel SMU for MOSFET testing with Test script processor and IV software: 2 nos (one setup for three students)
- Resistivity and Conductivity Setup – #2 setups
- I-V SMU analyser
- Four Point Collinear Resistivity Measurement Setup
- Resistivity samples #2
- Conductivity Samples #2
- Inverter testing setup: power suppy #1, Scope with AFG and power application: #1no
- Xilinx /CAD: 5 no.
Course Outcomes:
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Text Books:
- Kamran Ehraghian, Dauglas A. Pucknell and Sholeh Eshraghiam, “Essentials of VLSI Circuits and Systems” – PHI, EEE, 2005 Edition.
- Neil H. E. Weste and David. Harris Ayan Banerjee,, “CMOS VLSI Design” – Pearson Education, 1999.
Reference Books:
- M.L. Bushnell and V.D. Agrawal, “Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits”, Kluwer Academic Publishers, 2004
- N.K. Jha and S.G. Gupta, “Testing of Digital Systems”, Cambridge University Press, 2003
- Etienne Sicard, Sonia Delmas Bendhia, “Basics of CMOS Cell Design”, TMH, EEE, 2005
For detailed syllabus of all the other subjects of Electronics & Telecommunication Engineering 5th Sem, visit ETE 5th Sem subject syllabuses for 2021 regulation.
For all Electronics & Telecommunication Engineering results, visit Anna University ETE all semester results direct link.