Very Large Scale Integration Practical detail TNDTE Diploma syllabus for Electronics And Communication Engineering (EC), M scheme is extracted from TNDTE official website and presented for diploma students. The course code (34057), and for exam duration, Teaching Hr/week, Practical Hr/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below. The syllabus PDFs can be downloaded from official website.
For all other electronics 5th sem syllabus for diploma m scheme tndte you can visit Electronics 5th Sem Syllabus for Diploma M Scheme TNDTE Subjects. The detail syllabus for very large scale integration practical is as follows.
Rationale:
VHDL is a versatile and powerful hardware description language which is useful for modeling digital systems at various levels of design abstraction. This language is for describing the structural, physical and behavioral characteristics of digital systems. Execution of a VHDL program results in a simulation of the digital system allows us to validate the design prior to fabrication of Digital Integrated circuit. This practical introduces basic on VHDL concepts and constructs. It introduces the VHDL from simulation cycle to synthesis level in combinational and sequential circuits.
Guidelines:
All the experiments given in the list of experiments should be completed and given for the end semester practical examination. In order to develop best skills in handling Instruments/Equipment and taking readings in the practical classes, every three students should be provided with a separate experimental setup fordoing experiments in the laboratory. The external examiners are requested to ensure that a single experimental question should not be given to more than three students while admitting a batch of 30 students during Board Examinations.
Allocation of Marks:
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List of Experiments:
- Simulation Of Vhdl Code For Combinational Circuit
- Simulation Of Vhdl Code For Arithmetic Circuits
- Simulation Of Vhdl Code For Multiplexer
- Simulation Of Vhdl Code For Demultiplexer
- Vhdl Implementation Of Multiplexer
- Vhdl Implementation Of Demultiplexer
- Vhdl Implementation Of 7 Segment Decoder
- Vhdl Implementation Of 7 Segment Decoder By Lut
- Vhdl Implementation Of Encoder
- Simulation Of Vhdl Code For Delay
- Vhdl Implementation For Blinking A Led
- Simulate A Vhdl Test Bench Code For Testing A Gate
- Vhdl Implementation For Blinking A Array Of Leds
- Vhdl Implementation Of A Speller With An Array Of Leds
- Vhdl Implementation Of 7 Segment Display
Optimize a 4 variable combinational function (SOP or POS), describe it in VHDL code and simulate it.
Example: F= ( 0,5,8,9,12) in sop or pos
Design and Develop the circuit for the following arithmetic function in VHDL Codes and Simulate it. Addition, Subtraction Multiplication (4 x 4 bits)
Design and develop a 2 bit multiplexer and portmap the same for developing upto 8 bit multiplexer.
Design and develop an 8 output demultiplexer. Simulate the same code in the software
Describe the code for a multiplexer and implement it in FPGA kit in which switches are connected for select input and for data inputs a LED is connected to the output.
Switches are connected for select inputs and a data input, Eight LEDs are connected to the output of the circuit.
Develop Boolean expression for 4 input variables and 7 output variables. Design and develop a seven segment decoder in VHDL for 7 equations. A seven segment display is connected to the output of the circuit. Four switches are connected to the input. The 4 bit input is decoded to 7 segment equivalent.
Develop a 7 segment decoder using Look up table. Describe the seven segment decoder in VHDL using developed Look up table. A seven segment display is connected to the output of the circuit. Four switches are connected to the input. The 4 bit input is decoded into 7 segment equivalent.
Design and develop HDL code for decimal (Octal) to BCD encoder. There will be10 input switches (or 8 switches) and 4 LEDs in the FPGA kit. The input given from switches and it is noted that any one of the switch is active. The binary equivalent for the corresponding input switch will be glowing in the LED as output.
Develop a VHDL code for making a delayed output for 1second or 2 seconds by assuming clock frequency provided in the FPGA Kit.
Develop a VHDL Code for delay and verify by simulating it. This delay output is connected to LED. Delay is adjusted such away LED blinks for every 1 or 2 seconds.
Develop a VHDL test bench code for testing any one of the simple gate. Simulate the test bench code in the HDL software.
Design and develop a VHDL Code for 4 bit binary up counter. Four LEDs are connected at the output of the counter. The counter should up for every one seconds.
Design and develop VHDL Code for a 5 bit Johnson ring counter 4 bit The LEDs are connected at the output of the counter. The speller should work for every one seconds.
Design and develop a seven segment decoder in VHDL. Design and develop a 4 bit BCD counter, the output of the counter is given to seven segment decoder. A seven segment display is connected to the output of the decoder. The display shows 0,1, 2.. 9 for every one second
List of Equipments
FPGA KIT with atleast 10 switches for input, 8 LEDs for output, a 7 segment display, debounced push switch ( 2 Nos) for manual clock input and external clock source – 10Nos .
Note:
- Gate level or behavioral level or structural model can be used for all experiments.
- Manual for the FPGA Kit and interface kit can be given to students for the final exam.
For detail syllabus of all other subjects of BE Electronics, M scheme do visit Electronics 5th Sem syllabus for M scheme.
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