Full custom IC Design Detailed Syllabus for VLSI/ VLSI Design/VLSI System Design M.Tech first year second sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.
The detailed syllabus for Full custom IC Design M.Tech 2017-2018 (R17) first year second sem is as follows.
M.Tech. I Year II Sem.
UNIT – I : Introduction: Schematic fundamentals, Layout design, Introduction to CMOS VLSI manufacturing processes, Layers and connectivity, Process design rules Significance of full custom IC design, layout design flows.
UNIT – II : Advanced techniques for specialized building blocks Standard cell libraries, Pad cells and Laser fuse cells, Advanced techniques for building blocks, Power grid Clock signals
UNIT – III : Interconnect routing. Interconnect layout design, Special electrical requirements, Layout design techniques to address electrical characteristics.
UNIT – IV : Layout considerations due to process constraints Large metal via implementations, Step coverage rules, Special design rules, Latch-up and Guard rings, Constructing the pad ring, Minimizing Stress effects.
UNIT – V : Proper layout CAD tools for layout, Planning tools, Layout generation tools, Support tools.
TEXT BOOKS:
- Dan Clein, “CMOS IC Layout Concepts Methodologies and Tools”, Newnes, 2000.
- Ray Alan Hastings, “The Art of Analog Layout”, 2nd Edition, Prentice Hall, 2006
For all other M.Tech 1st Year 2nd Sem syllabus go to JNTUH M.Tech VLSI/ VLSI Design/VLSI System Design 1st Year 2nd Sem Course Structure for (R17) Batch.
All details and yearly new syllabus will be updated here time to time. Subscribe, like us on facebook and follow us on google plus for all updates.
Do share with friends and in case of questions please feel free drop a comment.