Digital System Design Syllabus VTU BE/B.Tech Electrical and Electronics Engineering III sem is covered here. This will help you get a complete picture of the modules in this subject including subtopics in each module. Further, information about exam marks, duration of the course and the credits is provided. The details are as follows.
| Subject Code | 15EE35 | IA Marks | 20 |
|---|---|---|---|
| Number of Lecture Hours/Week | 4 | Exam Marks | 80 |
| Total Number of Lecture Hours | 50 | Exam Hours | 3 |
CREDITS – 04
Digital System Design Syllabus VTU BE/B.Tech EEE
Course Objectives:
This course will enable students to:
- To impart the knowledge of combinational circuit design.
- To impart the knowledge of Sequential circuit design.
- To provide the basic knowledge about VHDL & its use.
| Modules | Teaching Hour | Revised Bloom’s Taxonomy (RBT) Level |
|---|---|---|
| Module -1 | _ | |
| Principles of combinational logic: Review of Boolean Algebra. Definition of combinational, Canonical forms, Generation of switching equations from truth tables, Karnaugh maps-3, 4 and 5 variables. Incompletely specified functions (Don’t care terms). Simplifying max – term equations. Quine -McClusky minimization technique, Quine – McClusky using don’t care terms, Reduced Prime Implicant tables, Map entered variables | 10 Hours | L1 – Remembering, L2 – Understanding, L3 – Applying. |
| Module -2 | _ | |
| Analysis and design of Combinational Logic: | 10 Hours | L1 – Remembering, L2 – Understanding, L3 – Applying, L4 – Analysing. |
| Module -3 | _ | |
| Sequential Circuits: Basic Bistable element, Latches, SR latch, Application of SR latch, A Switch debouncer. The SR latch, The gated SR latch. The gated D Latch, The Master-Slave Flip-Flops (Pulse-Triggered Flip-Flops): The master-slave SR Flip-Flops, The master-slave JK Flip-Flop, Edge Triggered Flip-flop: The Positive Edge-Triggered D Flip-Flop, Negative-Edge Triggered D Flip-Flop. Characteristic equations, Registers, Counters-Binary Ripple Counter, Synchronous Binary counters, Counters based on Shift Registers, Design of a Synchronous counters, Design of a Synchronous Mod-N counters using clocked JK FlipFlops Design of a Synchronous Mod-N counter using clocked D, T, or SR Flip-Flops | 10 Hours | L1 – Remembering, L2 – Understanding, L3 – Applying, L4 – Analysing. |
| Module -4 | _ | |
| Sequential Design: Introduction, Mealy and Moore models, State machine notation, synchronous sequential circuit analysis and design. Construction of state Diagrams, Counters Design. | 10 Hours | L1 – Remembering, L2 – Understanding, L3 – Applying, L4 – Analysing. |
| Module -5 | _ | |
| HDL: Introduction, A brief history of HDL, Structure of HDL Module, Operators, Data types, Types of Descriptions, Simulation and synthesis, Brief comparison of VHDL and Verilog. Data-Flow Descriptions: Highlights of Data flow descriptions, Structure of data-flow description, Data type-vectors. | 10 Hours | L1 – Remembering, L2 – Understanding, L3 – Applying. |
Course outcomes: After studying this course, students will be able to:
- Design and analyze combinational & sequential circuits
- Design circuits like adder, sub tractor, code converter etc.
- Understand counters and sequence generators.
Graduate Attributes (As per NBA)
- Engineering Knowledge Problem Analysis Ethics Question paper pattern:
- The question paper will have ten questions.
- Each full question is for 16 marks.
- There will be 2 full questions (with a maximum of four sub questions in one full question) from each module.
- Each full question with sub questions will cover the contents under a module.
- Students will have to answer 5 full questions, selecting one full question from each module.
Text/Reference Books
- Digital Logic Applications and Design John M Yarbrough Cengage Learning 2011
- Digital Principles and Design Donald D Givone McGraw Hill Education 1 st Edition, 2002
- Logic and computer design Fundamentals M. Morries Mano and Charles Kime Pearson Learning 4 th Edition, 2014
- Fundamentals of logic design Charles H Roth, JR and Larry L. Kinney Cengage Learning 6th Edition, 2013
- Fundamentals of Digital Circuits A. Anand Kumar PHI 3rd Edition, 2014
- Digital Logic Design and VHDL A.A.Phadke S.M.Deokar Wiley India 1st Edition, 2009
- Digital Circuits and Design D.P.Kothari J.S.Dhillon Pearson First Print 2015
- HDL Programming (VHDL and Verilog) Nazeih M. Botros Cengage Learning 1 st Edition, 2011
- Circuit Design and Simulation with VHDL Volnei A Pedroni PHI 2nd Edition,
For all other BE/B.Tech 3rd Sem Subject syllabus do follow VTU 3rd Sem BE / B.Tech Syllabus CBCS (2015-16) Scheme for Electrical and Electronics Engineering Group.
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