Digital Design and HDL Syllabus for VTU BE/B.Tech Biomedical Engineering third sem complete syllabus covered here. This will help you understand complete curriculum along with details such as exam marks and duration. The details are as follows.
| Subject Code | 15 EI/BM/ML 34 | IA Marks | 20 |
|---|---|---|---|
| Number of Lecture Hours/Week | 04 | Exam Marks | 80 |
| Total Number of Lecture Hours | 50 | Exam Hours | 3 |
CREDITS – 04
Course Objectives: This course will enable the students to
- To impart the concepts of simplifying Boolean expression using K-map techniques and provide an understanding of logic families
- To impart the concepts of designing and analyzing combinational logic circuits
- To provide an understanding for the concepts of HDL-Verilog, data flow and behavioral models for the design of digital systems.
- To impart design methods and analysis of sequential logic circuits
| MODULES | TEACHING HOURS | REVISED BLOOM’S TAXONOMY (RBT) LEVEL |
|---|---|---|
| Module -1 | _ | |
| Principles of combinational logic: Definition of combinational logic, Canonical forms, Generation of switching equations from truth tables, Karnaugh maps- up to 4 variables, Quine-McCluskey minimization technique Introduction to Verilog: Structure of Verilog module, Operators, data types, Styles of description- Data flow description, Behavioral description, Implement logic gates, half adder and full adder using Verilog data flow description. | 10 Hours | L2,L3,L4 |
| Module -2 | _ | |
| Combinational Functions: | 10 Hours | L1,L2,L3 |
| Module -3 | _ | |
| Analysis and design of combinational logic: Encoders: Binary coded decimal codes, Binary – Gray vice versa, BCD – Excess 3 Encoders: Realization and Priority Encoders, Decoders: BCD – Decimal, BCD – Seven segment, Seven segment display. Verilog behavioral description of Encoders (8 to 3 with priority and without priority), Decoders (2 to 4). | 10 Hours | L1,L2 |
| Module -4 | _ | |
| Sequential Logic Circuits-1:Latches and Flip-Flops: SR-latch, D-latch, D flip-flop, JK flip-flop, T flip- flop Master slave FF, Edge trigger and Pulse trigger FF , Registers and Shift Registers: PISO, PIPO, SISO,SIPO, Right shift and left shift, Universal Shift register. Verilog behavioral description of latches (D-latch, SR latch) and flip-flops (D, T, JK, SR flip-flops). | 10 Hours | L2,L3,L6 |
| Module -5 | _ | |
| Counters, design and their applications: Counters-Binary ripple counters, Synchronous binary counters, Modulo N counters – Synchronous and Asynchronous counters. Verilog behavioral description of Synchronous and Asynchronous counters, sequential counters. Synthesis of Verilog: Mapping process in the hardware domain- Mapping of signal assignment, variable assignment, if statements, else-if statements, loop statements | 10 Hours | L2,L3,L4,L 6 |
Revised Bloom’s Taxonomy Levels: L1 – Remembering, L2 – Understanding, L3 – Applying, L4 – Analysing, L5 – Evaluating, and L6 – Creating
Course Outcomes: After studying this course, students will able to:
- Simplify Boolean functions using K-map and Quine-McCluskey minimization technique
- Analyze, design and write verilog code for combinational logic circuits. (MUX, De-MUX, adder and subtractor, and comparator circuits)
- Analyze and design code converters, encoders and decoders.
- Analyze and design of synchronous sequential circuits
- Analyze sequential circuits, Moore/Mealy machines
Graduate Attributes (as per NBA)
- Engineering knowledge
- Problem analysis
- Design & Development of Solutions
- Modern tool usage
Question Paper Pattern:
- The question paper will have TEN questions.
- Each full question consists of 16 marks.
- There will be 2 full questions (with maximum of FOUR sub questions) from each module.
- Each full question will have sub questions covering all the topics under a module.
- The students will have to answer 5 full questions, selecting one full question from each module.
Text Books:
- Digital Logic Applications and Design by John M Yarbrough, Thomson Learning,2001 (Modules 1,2,3,4,5 –Logic design)
- HDL Programming VHDL and Verilog by Nazeih M. Botros, 2009 reprint, Dreamtech press.(Modules 1,2,3,4,5 Verilog description)
Reference Books:
- Charles H Roth, Jr., “Fundamentals of logic design”, Cengage Learning
- Digital Principals and Design – Donald D Givone,12th reprint, TMH,2008
- Logic Design, Sudhakar Samuel, Pearson/ Saguine, 2007
- Fundamentals of HDL- Cyril P R Pearson/Sanguin 2010
For all other BE/B.Tech 3rd Sem Subject syllabus do follow VTU 3rd Sem BE / B.Tech Syllabus CBCS (2015-16) Scheme for Biomedical Engineering Group.
For all other BE/B.Tech 3rd Sem Subject syllabus do follow VTU 3rd Sem BE / B.Tech Syllabus CBCS (2015-16) Scheme for Electronics and Instrumentation Engineering Group.
For all other BE/B.Tech 3rd Sem Subject syllabus do follow VTU 3rd Sem BE / B.Tech Syllabus CBCS (2015-16) Scheme for Medical Electronics Group.
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