18NT821: Digital Systems Design Nano Syllabus for BE 8th Sem 2018 Scheme VTU (Professional Elective-4)

Digital Systems Design detailed Syllabus for Nano Technology (Nano), 2018 scheme has been taken from the VTUs official website and presented for the VTU students. For Course Code, Subject Names, Teaching Department, Paper Setting Board, Theory Lectures, Tutorial, Practical/Drawing, Duration in Hours, CIE Marks, Total Marks, Credits and other information, visit full semester subjects post given below. The Syllabus PDF files can also be downloaded from the official website of the university.

For all the other VTU Nano 8th Sem Syllabus for BE 2018 Scheme, visit Nano Technology 8th Sem 2018 Scheme.

For all the (Professional Elective-4) subjects refer to Professional Elective-4 Scheme. The detail syllabus for digital systems design is as follows.

Course Learning Objectives:

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Module-1

FUNDAMENTALS OF DIGITAL SYSTEMS: Combinational circuits, sequential circuits, basic gates, realization of logic using NAND, NOR and 2:1 Multiplexers, design of half adder, full adders, full subtractor, 1-bit comparator, decoders and encoders. Introduction to Verilog HDL, coding types, behavioural, structural and data flow, modelling of basic gates, half adder and full adder using Verilog HDL.

Module-2

DESIGNING WITH COMBINATIONAL CIRCUITS: 4-bit Ripple carry adder, 4-bit carry look ahead adder, 4-bit carry select adder, 4-bit comparator using 2-bit comparator, seven segment display controllers using encoders and decoders, parity generators and 3-bit shifters/rotators using multiplexers, barrel shifter/rotator using 2:1 multiplexer. Writing Verilog code for 4-bit ripple carry adder, parity generators.

Module-3

Module-4

DIGITAL CIRCUIT DESIGN USING MOS TRANSISTOR: MOS transistor, NMOS and PMOS transistor, CMOS inverter circuit, CMOS circuit design for NAND, NOR, AND, OR, XOR, XNOR gate, transmission gate using CMOS, 2:1 multiplexer design using CMOS transmission gate, 1-bit latch using CMOS (2:1 multiplexer), 1-bit flip flop using CMOS latch. Introduction to propagation delay, rise time, fall time, noise margin for CMOS inverter. Introduction to power dissipation in CMOS circuits, dynamic power, static power, leakage power.

Module-5

SUBSYSTEM DESIGN AND MODELLING: writing Verilog code using data flow description for D-latch, JK-flip flop, counters, 2-Bit Magnitude comparators, 4×4 memory with read and write ports, behavioural model for 4-bit ALU design using Verilog HDL, writing test bench wave forms for functional verification of 4-bit adders and ALU. Introduction to programmable logics such as PLA, PAL and FPGAs.

Course Outcomes:

Question Paper Pattern:

The question paper will have ten full questions carrying equal marks. Each full question consisting of 16 marks.
There will be two full questions (with a maximum of four sub questions) from each module.
Each full question will have sub question covering all the topics under a module.
The students will have to answer five full questions, selecting one full question from each module.

Text Books:

HDL programing fundamental: VHDL and Verilog N. Botros Cengage learning First Edition, 2007
Digital Fundamentals Thomas L. Floyd Pearson Publications First Edition, 2012

Reference Books:

For the detail Syllabus of all other subjects of BE (Nano) 8th Sem, visit Nano Technology 8th Sem Subjects.

For all (CBSE & Non-CBSC) BE/B.Tech results, visit VTU BE/B.Tech all semester results.

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