VLSI Laboratory Detailed Syllabus for Embedded Systems & VLSI Design/ VLSI and Embedded Systems/ Electronics Design Technology M.Tech first year first sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.
The detailed syllabus for VLSI Laboratory M.Tech 2017-2018 (R17) first year first sem is as follows.
M.Tech. I Year I Sem.
Note: Minimum of 10 programs from Part –I and 2 programs from Part -II are to be conducted. Design and implementation of the following CMOS digital/analog circuits must be carried out using Cadence / Mentor Graphics / Synopsys / Equivalent CAD tools. The design shall include Gatelevel design, Transistor-level design, Hierarchical design, Verilog HDL/VHDL design, Logic synthesis, Simulation and verification.
Part –I: VLSI Front End Design programs:
Programming can be done using any complier. Down load the programs on FPGA/CPLD boards and performance testing may be done using pattern generator (32 channels) and logic analyzer apart from verification by simulation with any of the front end tools.
- HDL code to realize all the logic gates
- Design and Simulation of adder, Serial Binary Adder, Multi Precession Adder, Carry
- Look Ahead Adder.
- Design of 2-to-4 decoder
- Design of 8-to-3 encoder (without and with parity)
- Design of 8-to-1 multiplexer
- Design of 4 bit binary to gray converter
- Design of Multiplexer/ Demultiplexer, comparator
- Design of Full adder using 3 modeling styles
- Design of flip flops: SR, D, JK, T
- Design of 4-bit binary, BCD counters ( synchronous/ asynchronous reset) or any sequence counter
- Design of a N- bit Register of Serial- in Serial –out, Serial in parallel out, Parallel in
- Serial out and Parallel in Parallel Out.
- Design of Sequence Detector (Finite State Machine- Mealy and Moore Machines).
- Design of 4- Bit Multiplier, Divider.
- Design of ALU to Perform – ADD, SUB, AND-OR, 1’s and 2’s Compliment, Multiplication and Division.
- Design of Finite State Machine.
- Implementing the above designs on Xilinx/Altera/Cypress/equivalent based FPGA/CPLD kits.
Part –II: VLSI Back End Design programs:
Design and implementation of the following CMOS digital/analog circuits using Cadence / Mentor Graphics / Synopsys / Equivalent CAD tools. The design shall include Gate-level design/Transistorlevel design/Hierarchical design/Verilog HDL or VHDL design, Logic synthesis, Simulation and verification, Scaling of CMOS Inverter for different technologies, study of secondary effects (temperature, power supply and process corners), Circuit optimization with respect to area, performance and/or power, Layout, Extraction of parasitic and back annotation, modifications in circuit parameters and layout consumption, DC/transient analysis, Verification of layouts (DRC, LVS).
- Introduction to layout design rules
- Layout, physical verification, placement & route for complex design, static timing analysis, IR drop analysis and crosstalk analysis of the following:
- Basic logic gates
- CMOS inverter
- CMOS NOR/ NAND gates
- CMOS XOR and MUX gates
- CMOS 1-bit full adder
- Static / Dynamic logic circuit (register cell)
- Latch
- Pass transistor
3. Layout of any combinational circuit (complex CMOS logic gate)- Learning about data paths
For all other M.Tech 1st Year 1st Sem syllabus go to JNTUH M.Tech Embedded Systems & VLSI Design/ VLSI and Embedded Systems/ Electronics Design Technology 1st Year 1st Sem Course Structure for (R17) Batch.
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