Test and Testability detailed syllabus for Electronics & Communication Engineering (ECE), R18 regulation has been taken from the JNTUHs official website and presented for the students of B.Tech Electronics & Communication Engineering branch affiliated to JNTUH course structure. For Course Code, Course Titles, Theory Lectures, Tutorial, Practical/Drawing, Credits, and other information do visit full semester subjects post given below. The syllabus PDF files can also be downloaded from the universities official website.
For all the other ECE 4th Year 2nd Sem Syllabus for B.Tech R18 Regulation JNTUH scheme, visit Electronics & Communication Engineering 4th Year 2nd Sem R18 Scheme.
For all the (Professional Elective-6) subjects refer to Professional Elective-6 Scheme. The detail syllabus for test and testability is as follows.
Prerequisite:
Switching Theory and Logic Design, Digital System Design with PLDS
Course Objective:
For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
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Course Outcome:
On completion of this course the student will be able to:
- To acquire the knowledge of fundamental concepts in fault and fault diagnosis
- Test pattern generation using LFSR and CA
- Design for testability rules and techniques for combinational circuits
- Introducing scan architectures
Unit – I
Need for testing, the problems in digital Design testing, the problems in Analog Design testing, the problems in mixed analog/digital design testing, design for test, printed-circuit board (PCB) testing, software testing, Fault in Digital Circuits: General Introduction, Controllability and Observability, Fault Models, stuck at faults, bridging faults, CMOS technology considerations, intermittent faults.
Unit – II
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Unit – III
Pseudorandorn test pattern generators, Design of test pattern generator usingLinear feedback shift registers (LFSRs) and cellular automata(CAs).
Unit – IV
Design for Testability for combinational circuits: Basic Concepts of testability, controllability and observability, the Reed Muller�s expansion techniques, use of control logic and syndrome testable designs.
Unit – V
For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier..
Text Books:
- Fault Tolerant and Fault Testable Hardware Design-Parag K. Lala, 1984, PHI.
- VLSI Testing digital and Mixed analogue/digital techniques-Stanley L. Hurst, IEE Circuits, Devices and Systems series 9, 1998.
Reference Books:
For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier..
For detail syllabus of all other subjects of B.Tech Electronics & Communication Engineering 4th Year 2nd Sem , visit ECE 4th Year 2nd Sem syllabus subjects.
For B.Tech Electronics & Communication Engineering (ECE) 4th Year results, visit JNTUH B.Tech Electronics & Communication Engineering semester results direct link.