EC821PE: System On Chip Architecture ECE Syllabus for B.Tech 4th Year 2nd Sem R18 Regulation JNTUH (Professional Elective-6)

System On Chip Architecture detailed syllabus for Electronics & Communication Engineering (ECE), R18 regulation has been taken from the JNTUHs official website and presented for the students of B.Tech Electronics & Communication Engineering branch affiliated to JNTUH course structure. For Course Code, Course Titles, Theory Lectures, Tutorial, Practical/Drawing, Credits, and other information do visit full semester subjects post given below. The syllabus PDF files can also be downloaded from the universities official website.

For all the other ECE 4th Year 2nd Sem Syllabus for B.Tech R18 Regulation JNTUH scheme, visit Electronics & Communication Engineering 4th Year 2nd Sem R18 Scheme.

For all the (Professional Elective-6) subjects refer to Professional Elective-6 Scheme. The detail syllabus for system on chip architecture is as follows.

Prerequisite:

Embedded System Design

Course Objective:

For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
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Course Outcome:

• Expected to understand SOC Architectural features.
• To acquire the knowledge on processor selection criteria and limitations
• To acquires the knowledge of memory architectures on SOC.
• To understands the interconnection strategies and their customization on SOC.

Unit – I

Introduction to the System Approach: System Architecture, Components of the system, Hardware and Software, Processor Architectures, Memory and Addressing. System level interconnection, An approach for SOC Design, System Architecture and Complexity.

Unit – II

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Unit – III

Memory Design for SOC: Overview of SOC external memory, Internal Memory, Size, Scratchpads and Cache memory, Cache Organization, Cache data, Write Policies, Strategies for line replacement at miss time, Types of Cache, Split – I , and D – Caches , Multilevel Caches, Virtual to real translation , SOC Memory System , Models of Simple Processor – memory interaction.

Unit – IV

Interconnect Customization: Inter Connect Architectures, Bus: Basic Architectures, SOC Standard Buses, Analytic Bus Models, Using the Bus model, Effects of Bus transactions and contention time. SOC Customization:

Unit – V

For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
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Text Books:

1. Computer System Design System-on-Chip by Michael J. Flynn and Wayne Luk, Wiely India Pvt. Ltd.
2. ARM System on Chip Architecture – Steve Furber -2nd Eed., 2000, Addison Wesley Professional.

Reference Books:

For the complete syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdfs platform to make students’s lives easier.
.

For detail syllabus of all other subjects of B.Tech Electronics & Communication Engineering 4th Year 2nd Sem , visit ECE 4th Year 2nd Sem syllabus subjects.

For B.Tech Electronics & Communication Engineering (ECE) 4th Year results, visit JNTUH B.Tech Electronics & Communication Engineering semester results direct link.