Digital Electronics Laboratory Syllabus for VTU BE/B.Tech Electronics and Communication /Telecommunication Engineering third sem complete syllabus covered here. This will help you understand complete curriculum along with details such as exam marks and duration. The details are as follows.
| Laboratory Code | 15ECL38 | IA Marks | 20 |
|---|---|---|---|
| Number of Lecture Hours/Week | 01Hr Tutorial (Instructions) + 02 Hours Laboratory | Exam Marks | 50 |
| Exam Hours | 3 |
CREDITS – 02
Course Objectives:
This laboratory course enables students to get practical experience in design, realisation and verification of
- Demorgan’s Theorem, SOP, POS forms
- Full/Parallel Adders, Subtractors and Magnitude Comparator
- Multiplexer using logic gates
- Demultiplexers and Decoders
- Flip-Flops, Shift registers and Counters
| Laboratory Experiments: NOTE: The experiments are to be carried using discrete components only. |
Revised Bloom’s Taxonomy (RBT) Level |
|---|---|
| 1. Verify (a) Demorgan’s Theorem for 2 variables. (b) The sum-of product and product-of-sum expressions using universal gates. |
L1, L2, L3, L4 |
| Download iStudy App (No Ads, No PDFs) for complete VTU syllabus, results, timetables and all other updates. | L3, L4 |
| 3. Design and implement 4-bit Parallel Adder/ subtractor using IC 7483. | L3, L4, L5 |
| 4. Design and Implementation of 4-bit Magnitude Comparator using IC 7485. | L3, L4, L5 |
| 5. Realize (a) 4:1 Multiplexer using gates. (b) 3-variable function using IC 74151(8:1MUX). |
L2, L3, L4 |
| 6. Realize 1:8 Demux and 3:8 Decoder using IC74138. | L2, L3, L4 |
| 7. Realize the following flip-flops using NAND Gates. (a) Clocked SR Flip-Flop (b) JK Flip-Flop. |
L2, L3 |
| 8. Realize the following shift registers using IC7474 (a) SISO (b) SIPO (c) PISO (d)PIPO. |
L2, L3 |
| 9. Realize the Ring Counter and Johnson Counter using IC7476. | L2, L3 |
| 10. Realize the Mod-N Counter using IC7490. | L2, L3 |
| 11. Simulate Full- Adder using simulation tool | L2, L3, L4 |
| 12. Simulate Mod-8 Synchronous UP/DOWN Counter using simulation tool. | L2, L3, L4 |
Course outcomes: On the completion of this laboratory course, the students will be able to:
- Demonstrate the truth table of various expressions and combinational circuits using logic gates.
- Design, test and evaluate various combinational circuits such as adders, subtractors, comparators, multiplexers and demultiplexers.
- Construct flips-flops, counters and shift registers.
- Simulate full adder and up/down counters.
Graduate Attributes (as per NBA)
- Engineering Knowledge.
- Problem Analysis.
- Design/Development of solutions.
Conduct of Practical Examination:
- All laboratory experiments are to be included for practical examination.
- Students are allowed to pick one experiment from the lot.
- Strictly follow the instructions as printed on the cover page of answer script for breakup of marks.
- Change of experiment is allowed only once and 15% Marks allotted to the procedure part to be made zero.
NOTE: For experiment 11 and 12 any open source or licensed simulation tool may be used.
For all other BE/B.Tech 3rd Sem Subject syllabus do follow VTU 3rd Sem BE / B.Tech Syllabus CBCS (2015-16) Scheme for Electronics & Communication and Telecommunication Engineering Group.
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