MOSFETs and Digital Circuits Syllabus for VTU BE/B.Tech Nano Technology third sem complete syllabus covered here. This will help you understand complete curriculum along with details such as exam marks and duration. The details are as follows.
| Subject Code | 15NT34 | IA Marks | 20 |
|---|---|---|---|
| Number of Lecture Hours/Week | 04 | Exam Marks | 80 |
| Total Number of Lecture Hours | 50 | Exam Hours | 3 |
CREDITS – 04
Course objectives:This course will enable students to:
- Describe, Illustrate and Analyze MOS transistor theory, MOS VI characteristics, NMOS and PMOS transistor and CMOS technology
- Define and describe realization of digital circuits using CMOS technology
- Describe, Demonstrate, Analyze and Design of Mealy and Moore Models, Synchronous Sequential Circuits, State diagrams and Registers and Counters.
| MODULES | TEACHING HOURS | REVISED BLOOM’S TAXONOMY (RBT) LEVEL |
|---|---|---|
| Module -1 | _ | |
| MOSFETs Field – Effect Transistors: Introduction, Construction and Characteristics of JFETs, Transfer Characteristics- Derivation, Applying Schokley’s Equation, Depletion Type MOSFET: Basic Construction, Types of MOS, NMOS, PMOS, Basic Operation and Characteristics, VI Characteristics, Fabrication process of MOS transistors, N-well process, twin well process, SOI process MOSFET models: Small signal model, introduction to second order effects: body effect, channel length modulation, sub threshold conduction | 10 Hours | L1,L2 |
| Module -2 | _ | |
| 10 Hours | L1, L2 | |
| Module -3 | _ | |
| CMOS sequential circuits 1-bit Latch, SR latch, gated SR latch, D-latch, positive triggered latch, negative triggered latch, master-slave register, flip flop, edge triggered register, JK flip flop, Latch vs Registers Timing Diagram: Timing definitions, setup time, hold time, clock to q delay, maximum clock frequency, mux based latch, CMOS Schmitt trigger, ring oscillator | 10 Hours | L1, L2, L3 |
| Module -4 | _ | |
| Registers and Counters Registers: Introduction, Registers: Four Bit Latch, Shift Register, Serial In Serial Out Shift Register: Left-Shift Serial-In Serial-Out Register with D Flip-Flop, Serial-In Parallel-Out Shift Register, Parallel-In Serial-Out Shift Register: PISO Left-Shift Register, Ring Counter, Johnson Counter. Counters: Introduction, Synchronous Counter, Modulus-4 Synchronus Up Counter, Modulus-4 Synchronus Down Counter, Modulus-4 Synchronus Up/Down Counter, Modulus-8 Synchronus Up Counter, Modulus-8 Synchronus Down Counter, Modulus-8 Synchronus Up/ Down Counter. | 10 Hours | L1, L2, L3, L4 |
| Module -5 | _ | |
| Finite State Machines: Introduction, mealy machine, Moore machines, sequence detector, examples of sequence detector of 4 bit sequence, representing counters using FSM diagrams | 10 Hours | L1, L2, L3, L4 |
Course outcome: After studying this course, students will be able to:
- Discuss MOSFETs and its properties, CMOS technology and importance of MOS models
- Use CMOS technology and realize combinational and sequential digital circuits
- Design complex digital circuits and state machines
Graduate Attributes (as per NBA):
- Engineering Knowledge.
- Problem Analysis.
- Design / development of solutions (partly).
- Interpretation of data.
Question paper pattern:
- The question paper will have ten questions.
- Each full Question consisting of 16 marks
- There will be 2 full questions (with a maximum of four sub questions) from each module.
- Each full question will have sub questions covering all the topics under a module.
- The students will have to answer 5 full questions, selecting one full question from each module.
Text Books:
- Neil H.E. Weste, Kamran Eshraghian, Principle of CMOS and VLSI Design A Systems Perspective 2nd Edition, Addison Wesley(Module 1 to Module 3)
- D. P. Kothari and J. S Dhillon, “Digital Circuits and Design”, Pearson, 2016, ISBN:9789332543539 (Module 4 and Module 5)
Reference Books:
- Donald D. Givone, “Digital Principles and Design”, McGraw Hill.
- Sung-Mo (Steve) Kang, Yusuf Leblebici, CMOS DIGITAL INTEGRATED CIRCUITS ANALYSIS & DESIGN3rd Edi=on, Mc Graw-Hill
- David A. Bell, “Electronic Devices and Circuits”, Oxford University Press.
For all other BE/B.Tech 3rd Sem Subject syllabus do follow VTU 3rd Sem BE / B.Tech Syllabus CBCS (2015-16) Scheme for Nano Technology Group.
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