Digital Electronics Lab Lab Syllabus for VTU BE/B.Tech Nano Technology third sem complete syllabus covered here. This will help you understand complete curriculum along with details such as exam marks and duration. The details are as follows.
| Subject Code | 15NTL38 | IA Marks | 20 |
|---|---|---|---|
| Number of Lecture Hours/Week | 01Hr Tutorial (Instructions) + 02 Hours Laboratory | Exam Marks | 50 |
| Exam Hours | 3 |
CREDITS – 03
Course objectives: This laboratory course enables students to:
- get practical experience in design, realisation and verification of Demorgan’s Theorem, Full/Parallel Adders and Subtractors, Multiplexer using logic gates, Demux and Decoder, Flip-Flops, Shift registers and Counters
- model, simulate and verify functionality of CMOS digital circuits
| Laboratory Experiments:NOTE: Use discrete components to test and verify the logic gates. Multisim may be used for designing the gates along with the above. | Revised Bloom’s Taxonomy (RBT) Level |
|---|---|
| 1. To verify (a) Demorgan’s Theorem for 2 variables (b) The sum-of product and product-of-sum expressions using universal gates. | L1, L2, L3 |
| L5, L6 | |
| 3. To design and implement 4-bit Parallel Adder/ subtractor using IC 7483. | L5, L6 |
| 4. To realize (a) 4:1 Multiplexer using gates (b) 3-variable function using IC 74151(8:1 MUX) (c) 1:8 Demux and 3:8 Decoder using IC74138 | L2, L3 |
| 5. To realise the following flip-flops using NAND Gates. (a) Clocked SR Flip-Flop (b) JK Flip-Flop | L2, L3 |
| 6. To realize the following shift registers using IC7474 (a) SISO (b) SIPO (c)PISO (d) PIPO | L2, L3 |
| 7. To realize the Ring Counter and Johnson Counter using IC7476 | L2, L3 |
| 8. To realize the Mod-N Counter using IC7490 | L2, L3 |
| 9. To capture CMOS inverter schematic and check for its functionality (selecting suitable technology 130nm and below, connecting 0.01pF of load capacitance and setting lengths & widths of transistor geometries) | L4, L5, L6 |
| 10. To capture schematic of NAND, NOR, AND using NAND and Inverter, OR using NOR & Inverter. Verify functionality of gates using CMOS logic, measure propagation delay of gates by setting widths of transistors | L4, L5, L6 |
| 11. To capture schematic of 2:1 multiplexer using CMOS transmission gates and verify its functionality, extend the design for 4:1 multiplexer | L4, L5, L6 |
| 12. To capture schematic of XOR gate, XNOR gate, multiplexer based latch, master slave register and verify its functionality | L4, L5, L6 |
Course outcomes: On the completion of this laboratory course, the students will be able to:
- Design, Test and Evaluate various combinational circuits such as adders, subtractors, multipliers, comparators, parity generators, multiplexers and de-Multiplexers.
- Construct flips-flops, counters and shift registers and verify its functionality
- Model and verify CMOS digital circuits using MOS transistors
Graduate Attributes (as per NBA)
- Engineering Knowledge.
- Problem Analysis.
- Design/Development of solutions.
Conduct of Practical Examination:
- All laboratory experiments are to be included for practical examination.
- Students are allowed to pick one experiment from the lot.
- Strictly follow the instructions as printed on the cover page of answer script for breakup of marks.
- Change of experiment is allowed only once and 15% Marks allotted to the procedure part to be made zero.
Reference Book ( For 1 to 6 experiments):
- K. A. Navas, “Electronics Lab Manual”, Volume I, PHI, 5th Edition, 2015, ISBN:9788120351424
Reference Book ( For 9 to 12 experiments):
- Cyril Prasanna Raj P., “CMOS digital circuit design manual”, Volume 1, MSEC E-publication, Edition 2016
For all other BE/B.Tech 3rd Sem Subject syllabus do follow VTU 3rd Sem BE / B.Tech Syllabus CBCS (2015-16) Scheme for Nano Technology Group.
For more information about all VTU updates please stay connected to us on FB and don’t hesitate to ask any questions in the comment.