Analog and Digital Electronics Syllabus for VTU BE/B.Tech Computer Science Engineering & Information Science Engineering third sem complete syllabus covered here. This will help you understand complete curriculum along with details such as exam marks and duration. The details are as follows.
| Subject Code | 15CS32 | IA Marks | 20 |
|---|---|---|---|
| Number of Lecture Hours/Week | 4 | Exam Marks | 80 |
| Total Number of Lecture Hours | 50 | Exam Hours | 3 |
CREDITS – 04
Course Objectives:
This course will enable students to:
- Recall and Recognize construction and characteristics of JFETs and MOSFETs and differentiate with BJT
- Demonstrate and Analyze Operational Amplifier circuits and their applications
- Describe, Illustrate and Analyze Combinational Logic circuits, Simplification of Algebraic Equations using Karnaugh Maps and Quine McClusky Techniques.
- Describe and Design Decoders, Encoders, Digital multiplexers, Adders and Subtractors, Binary comparators, Latches and Master-Slave Flip-Flops.
- Describe, Design and Analyze Synchronous and Asynchronous Sequential
- Explain and design registers and Counters, A/D and D/A converters.
| Modules | Teaching Hour | Text book |
|---|---|---|
| Module -1 | _ | |
| Field Effect Transistors: Junction Field Effect Transistors, MOSFETs, Differences between JFETs and MOSFETs, Biasing MOSFETs, FET Applications, CMOS Devices. Wave-Shaping Circuits: Integrated Circuit(IC) Multivibrators. Introduction to Operational Amplifier: Ideal v/s practical Opamp, Performance Parameters, Operational Amplifier Application Circuits:Peak Detector Circuit, Comparator, Active Filters, NonLinear Amplifier, Relaxation Oscillator, Current-To-Voltage Converter, Voltage-ToCurrent Converter. | 10 Hours | Ch 5: 5.2, 5.3, 5.5, 5.8, 5.9, 5.1.Ch13: 13.10.Ch 16: 16.3, 16.4. Ch 17: 7.12, 17.14, 17.15, 17.18, 17.19, 17.20, 17.21. |
| Module -2 | _ | |
| 10 Hours | Ch 2: 2.4, 2.5. Ch3: 3.2 to 3.11. | |
| Module -3 | _ | |
| Data-Processing Circuits: Multiplexers, Demultiplexers, 1-of-16 Decoder, BCD to Decimal Decoders, Seven Segment Decoders, Encoders, Exclusive-OR Gates, Parity Generators and Checkers, Magnitude Comparator, Programmable Array Logic, Programmable Logic Arrays, HDL Implementation of Data Processing Circuits. Arithmetic Building Blocks, Arithmetic Logic Unit Flip- Flops: RS Flip-Flops, Gated Flip-Flops, Edge-triggered RS FLIP-FLOP, Edge-triggered D FLIP-FLOPs, Edge-triggered JK FLIPFLOPs. | 10 Hours | Ch 4:- 4.1 to 4.9, 4.11, 4.12, 4.14.Ch 6:-6.7, 6.10.Ch 8:- 8.1 to 8.5. |
| Module -4 | _ | |
| Flip- Flops: FLIP-FLOP Timing, JK Master-slave FLIP-FLOP, Switch Contact Bounce Circuits, Various Representation of FLIP-FLOPs, HDL Implementation of FLIP-FLOP. Registers: Types of Registers, Serial In – Serial Out, Serial In – Parallel out, Parallel In – Serial Out, Parallel In – Parallel Out, Universal Shift Register, Applications of Shift Registers, Register implementation in HDL. Counters: Asynchronous Counters, Decoding Gates, Synchronous Counters, Changing the Counter Modulus. | 10 Hours | Ch 8: 8.6, 8.8, 8.9, 8.10, 8.13. Ch 9: 9.1 to 9.8. Ch 10: 10.1 to 10.4. |
| Module -5 | _ | |
| Counters: Decade Counters, Presettable Counters, Counter Design as a Synthesis problem, A Digital Clock, Counter Design using HDL. D/A Conversion and A/D Conversion: Variable, Resistor Networks, Binary Ladders, D/A Converters, D/A Accuracy and Resolution, A/D Converter-Simultaneous Conversion, A/D Converter-Counter Method, Continuous A/D Conversion, A/D Techniques, Dual-slope A/D Conversion, A/D Accuracy and Resolution. | 10 Hours | Ch 10: 10.5 to 10.9. Ch 12: 12.1 to 12.10. |
Course outcomes: After studying this course, students will be able to:
Acquire knowledge of
- JFETs and MOSFETs , Operational Amplifier circuits and their applications.
- Combinational Logic, Simplification Techniques using Karnaugh Maps, Quine McClusky technique.
- Operation of Decoders, Encoders, Multiplexers, Adders and Subtractors.
- Working of Latches, Flip-Flops, Designing Registers, Counters, A/D and D/A Converters.
Analyze the performance of
- JFETs and MOSFETs , Operational Amplifier circuits
- Simplification Techniques using Karnaugh Maps, Quine McClusky Technique.
- Synchronous and Asynchronous Sequential Circuits.
- Apply the knowledge gained in the design of Counters, Registers and A/D & D/A converters
Graduate Attributes (as per NBA)
- Engineering Knowledge
- Design/Development of Solutions(partly)
- Modern Tool Usage
- Problem Analysis
Question paper pattern:
- The question paper will have ten questions.
- There will be 2 questions from each module.
- Each question will have questions covering all the topics under a module.
- The students will have to answer 5 full questions, selecting one full question from each module.
Text Books:
- Anil K Maini, Varsha Agarwal: Electronic Devices and Circuits, Wiley, 2012.
- Donald P Leach, Albert Paul Malvino & Goutam Saha: Digital Principles and Applications, 8th Edition, Tata McGraw Hill, 2015
Reference Books:
- Stephen Brown, Zvonko Vranesic: Fundamentals of Digital Logic Design with VHDL, 2nd Edition, Tata McGraw Hill, 2005.
- R D Sudhaker Samuel: Illustrative Approach to Logic Design, Sanguine-Pearson, 2010.
- M Morris Mano: Digital Logic and Computer Design, 10 th Edition, Pearson, 2008.
For all other BE/B.Tech 3rd Sem Subject syllabus do follow VTU 3rd Sem BE / B.Tech Syllabus CBCS (2015-16) Scheme for Mechatronics Engineering Group.
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