Advanced Computer Architecture detail syllabus for Telecommunication Engineering (Telecom), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17EC754), and for exam duration, Teaching Hr/week, Practical Hr/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.
For all other telecom 7th sem syllabus for be 2017 scheme vtu you can visit Telecom 7th Sem syllabus for BE 2017 Scheme VTU Subjects. For all other Professional Elective-4 subjects do refer to Professional Elective-4. The detail syllabus for advanced computer architecture is as follows.
Course Objectives:
This course will enable students to:
- Understand the various parallel computer models and conditions of parallelism
- Explain the control flow, dataflow and demand driven machines
- Study CISC, RISC, superscalar, VLIW and multiprocessor architectures
- Understand the concept of pipelining and memory hierarchy design
- Explain cache coherence protocols.
Module 1
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Module 2
Program flow mechanisms: Control flow versus data flow, Data flow Architecture, Demand driven mechanisms, Comparisons of flow mechanisms. Principles of Scalable Performance: Performance Metrics and Measures, Parallel Processing Applications, Speedup Performance Laws, Scalability Analysis and Approaches.
Module 3
Speedup Performance Laws: Amdhals law, Gustafsons law, Memory bounded speed up model, Scalability Analysis and Approaches. Advanced Processors: Advanced processor technology, Instruction-set Architectures, CISC Scalar Processors, RISC Scalar Processors, Superscalar Processors, VLIW Architectures.
Module 4
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Module 5
Multiprocessor Architectures: Symmetric shared memory architectures, distributed shared memory architectures, models of memory consistency, cache coherence protocols (MSI, MESI, MOESI), scalable cache coherence, overview of directory based approaches, design challenges of directory protocols, memory based directory protocols, cache based directory protocols.
Course Outcomes:
At the end of the course, the students will be able to:
- Explain parallel computer models and conditions of parallelism
- Differentiate control flow, dataflow, demand driven mechanisms
- Explain the principle of scalable performance
- Discuss advanced processors architectures like CISC, RISC, superscalar and VLIW
- Understand the basics of instruction pipelining and memory technologies
- Explain the issues in multiprocessor architectures
Text Books:
Kai Hwang, Advanced computer architecture; TMH.
Reference Books:
- Kai Hwang and Zu, Scalable Parallel Computers Architecture; MGH.
- M.J Flynn, Computer Architecture, Pipelined and Parallel Processor Design; Narosa Publishing.
- D.A.Patterson, J.L.Hennessy, Computer Architecture :A quantitative approach; Morgan Kauffmann Feb, 2002.
For detail syllabus of all other subjects of BE Telecom, 2017 regulation do visit Telecom 7th Sem syllabus for 2017 Regulation.
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