3EC4-22: Digital System Design Lab Syllabus for ECE 3rd Sem 2021-22 Regulation RTU

Digital System Design Lab detailed syllabus for Electronics & Communication Engineering (ECE) for 2021-22 regulation curriculum has been taken from the Rajasthan Technical University official website and presented for the electronics & communication engineering students. For course code, course name, number of credits for a course and other scheme related information, do visit full semester subjects post given below.

For Electronics & Communication Engineering 3rd Sem scheme and its subjects, do visit ECE 3rd Sem 2021-22 regulation scheme. The detailed syllabus of digital system design lab is as follows.

List of Experiments:

Part A: Combinational Circuits

1. To verify the truth tables of logic gates: AND, OR, NOR, NAND, NOR, Ex-OR and Ex-NOR
2. To verify the truth table of OR, AND, NOR, Ex-OR, Ex-NOR logic gates realized using NAND & NOR gates.
3. To realize an SOP and POS expression.
4. To realize Half adder/ Subtractor& Full Adder/ Subtractor using NAND & NOR gates and to verify their truth tables
5. To realize a 4-bit ripple adder/ Subtractor using basic Half adder/ Subtractor& basic Full Adder/ Subtractor.
6. To design 4-to-1 multiplexer using basic gates and verify the truth table. Also verify the truth table of 8-to-1 multiplexer using IC
7. To design 1-to-4 demultiplexer using basic gates and verify the truth table. Also to construct 1-to-8 demultiplexer using blocks of 1-to-4 demultiplexer
8. To design 2×4 decoder using basic gates and verify the truth table. Also verify the truth table of 3×8 decoder using IC
9. Design & Realize a combinational circuit that will accept a 2421 BCD code and drive a TIL -312 seven-segment display

Part B: Sequential Circuits

1. Using basic logic gates, realize the R-S, J-K and D-flip flops with and without clock signal and verify their truth table.
2. Construct a divide by 2, 4 & 8 asynchronous counter. Construct a 4-bit binary counter and ring counter for a particular output pattern using D flip flop.
3. Design and construct unidirectional shift register and verify the
4. Design and construct BCD ripple counter and verify the function.
5. Design and construct a 4 Bit Ring counter and verify the function
6. Perform input/output operations on parallel in/Parallel out and Serial in/Serial out registers using clock. Also exercise loading only one of multiple values into the register using multiplexer.

Note: Minimum 6 experiments to be conducted from Part-A& 4 experiments to be conducted from Part-B.

Course Outcomes:

1. To minimize the complexity of digital logic circuits.
2. To design and analyse combinational logic circuits.
3. To design and analyse sequential logic circuits.
4. Able to implement applications of combinational & sequential logic circuits.

For detailed syllabus of all other subjects of Electronics & Communication Engineering, 2021-22 regulation curriculum do visit ECE 3rd Sem subject syllabuses for 2021-22 regulation.

For all Electronics & Communication Engineering results, visit Rajasthan Technical University electronics & communication engineering all semester results direct link.