CSC302: Digital Logic Design and Analysis Syllabus for CS 3rd Sem 2017 Pattern Mumbai University

Digital Logic Design and Analysis detailed syllabus scheme for Computer Engineering (CS), 2017 regulation has been taken from the University of Mumbai official website and presented for the Bachelor of Engineering students. For Course Code, Course Title, Test 1, Test 2, Avg, End Sem Exam, Team Work, Practical, Oral, Total, and other information, do visit full semester subjects post given below.

For all other Mumbai University Computer Engineering 3rd Sem Syllabus 2017 Pattern, do visit CS 3rd Sem 2017 Pattern Scheme. The detailed syllabus scheme for digital logic design and analysis is as follows.

Digital Logic Design and Analysis Syllabus for Computer Engineering SE 3rd Sem 2017 Pattern Mumbai University

Course Objectives:

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Course Outcomes:

At the end of the course student should be able-

1. To understand different number systems and their conversions.
2. To analyze and minimize Boolean expressions.
3. To design and analyze combinational circuits.
4. To design and analyze sequential circuits
5. To understand the basic concepts of VHDL.
6. To study basics of TTL and CMOS Logic families.

Module 1

Number Systems and Codes Introduction to number system and conversions: Binary, Octal, Decimal and Hexadecimal number Systems, Binary arithmetic: addition, subtraction (1s and 2s complement), multiplication and division. Octal and Hexadecimal arithmetic: Addition and Subtraction (7s and 8s complement method for octal) and (15s and 16s complement method for Hexadecimal). Codes: Gray Code, BCD Code, Excess-3 code, ASCII Code. Error Detection and Correction: Hamming codes. 8

Module 2

Boolean Algebra and Logic Gates: Theorems and Properties of Boolean Algebra, Boolean functions, Boolean function reduction using Boolean laws, Canonical forms, Standard SOP and POS form. Basic Digital gates: NOT , AND , OR , NAND , NOR , EXOR , EX-NOR, positive and negative logic, K-map method 2 variable, 3 variable, 4 variable, Dont care condition, Quine-McClusky Method, NAND-NOR Realization. 8

Module 3

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdf platform to make students’s lives easier.
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Module 4

Sequential Logic Design: Introduction: SR latch, Concepts of Flip Flops: SR, D, J-K, T, Truth Tables and Excitation Tables of all types, Race around condition, Master Slave J-K Flip Flops, Timing Diagram, Flip-flop conversion, State machines, state diagrams, State table, concept of Moore and Mealy machine. Counters : Design of Asynchronous and Synchronous Counters,Modulus of the Counters, UP- DOWN counter, Shift Registers: SISO, SIPO, PIPO, PISO Bidirectional Shift Register, Universal Shift Register, Ring and twisted ring/Johnson Counter, sequence generator. 15

Module 5

Introduction to VHDL: Introduction: Fundamental building blocks Library, Entity, Architecture, Modeling Styles, Concurrent and sequential statements, simple design examples for combinational circuits and sequential circuits. 6

Module 6

Digital Logic Families: Introduction: Terminologies like Propagation Delay, Power Consumption, Fan in and Fan out , current and voltage parameters, noise margin, with respect to TTL and CMOS Logic and their comparison 3

Text Books:

For the complete Syllabus, results, class timetable, and many other features kindly download the iStudy App
It is a lightweight, easy to use, no images, and no pdf platform to make students’s lives easier.
.

Reference Books:

1. Donald p Leach, Albert Paul Malvino,Digital principles and Applications,Tata McGraw
2. Yarbrough John M. , Digital Logic Applications and Design , Cengage Learning.
3. Douglas L. Perry, VHDL Programming by Example, Tata McGraw Hill.

Internal Assessment Assessment consists of two class tests of 20 marks each. The first class test is to be conducted when approx. 40% syllabus is completed and second class test when additional 40% syllabus is completed. Duration of each test shall be one hour.

Theory Examination:

1. Question paper will comprise of 6 questions, each carrying 20 marks.
2. The students need to solve total 4 questions.
3. Question No.1 will be compulsory and based on entire syllabus.
4. Remaining question (Q.2 to Q.6) will be selected from all the modules.

For detail syllabus of all other subjects of Computer Engineering (CS) 3rd Sem 2017 regulation, visit CS 3rd Sem Subjects syllabus for 2017 regulation.