Digital Logic Design detailed syllabus scheme for B.Tech Electronics & Telecommunication Engineering (ET), 2018-19 onwards has been taken from the DBATU official website and presented for the Bachelor of Technology students. For Subject Code, Course Title, Lecutres, Tutorials, Practice, Credits, and other information, do visit full semester subjects post given below.
For all other DBATU Syllabus for Electronics & Telecommunication Engineering 3rd Sem 2018-19, do visit ET 3rd Sem 2018-19 Onwards Scheme. The detailed syllabus scheme for digital logic design is as follows.
Digital Logic Design Syllabus for Electronics & Telecommunication Engineering (ET) 2nd Year 3rd Sem 2018-19 DBATU
Course Objectives:
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Course Outcomes:
On completion of the course, students will be able to:
- Use the basic logic gates and various reduction techniques of digital logic circuit in detail.
- Design combinational and sequential circuits.
- Design and implement hardware circuit to test performance and application.
- Understand the architecture and use of VHDL for basic operations and Simulate using simulation software.
UNIT – 1 Combinational Logic Design
Standard representations for logic functions, k map representation of logic functions (SOP and POS forms), minimization of logical functions for min-terms and max-terms (upto 4 variables), dont care conditions, Design Examples: Arithmetic Circuits, BCD – to – 7 segment decoder, Code converters. Adders and their use as subtractor, look ahead carry, ALU, Digital Comparator, Parity generators/checkers, Design of Multiplexers and Demultiplexers, Decoders.
UNIT – 2 Sequential Logic Design
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UNIT – 3 State Machines
Basic design steps- State diagram, State table, State reduction, State assignment, Mealy and Moore machines representation, Implementation, finite state machine implementation, Sequence detector.
UNIT – 4 Digital Logic Families
Classification of logic families, Characteristics of digital ICs-Speed of operation, power dissipation, figure of merit, fan in, fan out, current and voltage parameters, noise immunity, operating temperatures and power supply requirements. TTL logic, Operation of TTL NAND gate, active pull up, wired AND, open collector output, unconnected inputs. Tri-State logic. CMOS logic – CMOS inverter, NAND, NOR gates, unconnected inputs, wired logic, open drain output. Interfacing CMOS and TTL, Comparison table of Characteristics of TTL, CMOS, ECL, RTL, I2L and DCTL
UNIT – 5 Programmable Logic Devices and Semiconductor Memories
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UNIT – 6 Introduction to VHDL
Behavioral – data flow, and algorithmic and structural description, lexical elements, data objects types, attributes, operators; VHDL coding examples, combinational circuit design examples in VHDL and simulation.
Reference Books:
- R.P. Jain, Modern digital electronics!, 3rd edition, 12threprint Tata McGraw Hill Publication, 2007.
- M. Morris Mano, Digital Logic and Computer Design! 4th edition, Prentice Hall of India, 2013.
- Anand Kumar, Fundamentals of digital circuits! 1st edition, Prentice Hall of India, 2001.
- Pedroni V.A., Digital Circuit Design with VHDL, Prentice Hall India, 2nd 2001 Edition.
For detail syllabus of all other subjects of Electronics & Telecommunication Engineering (ET) 3rd Sem 2018-19 regulation, visit ET 3rd Sem Subjects syllabus for 2018-19 regulation.