M.Tech, Syllabus

JNTUH M.Tech 2017-2018 (R17) Detailed Syllabus Digital System Design

Digital System Design Detailed Syllabus for Embedded Systems M.Tech first year first sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.

The detailed syllabus for Digital System Design M.Tech 2017-2018 (R17) first year first sem is as follows.

M.Tech. I Year I Sem.

UNIT -I : Minimization and Transformation of Sequential Machines: The Finite State Model – Capabilities and limitations of FSM – State equivalence and machine minimization – Simplification of incompletely specified machines. Fundamental mode model – Flow table – State reduction – Minimal closed covers – Races, Cycles and Hazards.

UNIT -II : Digital Design: Digital Design Using ROMs, PALs and PLAs, BCD Adder, 32 – bit adder, State graphs for control circuits, Scoreboard and Controller, A shift and add multiplier, Array multiplier, Keypad Scanner, Binary divider.

UNIT -III : SM Charts: State machine charts, Derivation of SM Charts, Realization of SM Chart, Implementation of Binary Multiplier, dice game controller.

UNIT -IV : Fault Modeling & Test Pattern Generation: Logic Fault model – Fault detection & RedundancyFault equivalence and fault location –Fault dominance – Single stuck at fault model – Multiple stuck at fault models –Bridging fault model. Fault diagnosis of combinational circuits by conventional methods – Path sensitization techniques, Boolean Difference method – Kohavi algorithm – Test algorithms – D algorithm, PODEM, Random testing, Transition count testing, Signature analysis and test bridging faults.

UNIT -V : Fault Diagnosis in Sequential Circuits: Circuit Test Approach, Transition Check Approach – State identification and fault detection experiment, Machine identification, Design of fault detection experiment

TEXT BOOKS:

  • Charles H. Roth, “Fundamentals of Logic Design”, 5th Edition, Cengage Learning.
  •  Miron Abramovici, Melvin A. Breuer and Arthur D. Friedman, “Digital Systems Testing and Testable Design”, John Wiley & Sons Inc.
  • N. N. Biswas, “Logic Design Theory”, PHI

REFERENCE BOOKS:

  • Z. Kohavi , “Switching and Finite Automata Theory”, 2nd Edition, 2001, TMH
  • Morris Mano, M.D.Ciletti, “Digital Design”, 4th Edition, PHI.
  • Samuel C. Lee , “Digital Circuits and Logic Design”, PHI

For all other M.Tech 1st Year 1st Sem syllabus go to JNTUH M.Tech Embedded Systems 1st Year 1st Sem Course Structure for (R17) Batch.

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