- HDL code to realize all the logic gates
- Design and Simulation of adder, Serial Binary Adder, Multi Precession Adder, Carry
- Look Ahead Adder.
- Design of 2-to-4 decoder
- Design of 8-to-3 encoder (without and with parity)
- Design of 8-to-1 multiplexer
- Design of 4 bit binary to gray converter
- Design of Multiplexer/ Demultiplexer, comparator
- Design of Full adder using 3 modeling styles
- Design of flip flops: SR, D, JK, T
- Design of 4-bit binary, BCD counters ( synchronous/ asynchronous reset) or any sequence counter
- Design of a N- bit Register of Serial- in Serial –out, Serial in parallel out, Parallel in
- Serial out and Parallel in Parallel Out.
- Design of Sequence Detector (Finite State Machine- Mealy and Moore Machines).
- Design of 4- Bit Multiplier, Divider.
- Design of ALU to Perform – ADD, SUB, AND-OR, 1’s and 2’s Compliment,
- Multiplication, and Division.
- Design of Finite State Machine.
- Implementing the above designs on Xilinx/Altera/Cypress/equivalent based FPGA/CPLD kits
- Static and Dynamic Characteristics of CMOS Inverter
- Implementation of EX-OR gate using complementary CMOS, Psedo-NMOS, Dynamic and domino logic style
- Implementation of Full Adder using Transmission Gates
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