Digital IC Design Lab Detailed Syllabus for VLSI/ VLSI Design/VLSI System Design M.Tech first year first sem is covered here. This gives the details about credits, number of hours and other details along with reference books for the course.
The detailed syllabus for Digital IC Design Lab M.Tech 2017-2018 (R17) first year first sem is as follows.
M.Tech. I Year I Sem.
Part –I
Programming can be done using any complier. Down load the programs on FPGA/CPLD boards and performance testing may be done using pattern generator (32 channels) and logic analyzer apart from verification by simulation with any of the front end tools.
- HDL code to realize all the logic gates
- Design and Simulation of adder, Serial Binary Adder, Multi Precession Adder, Carry
- Look Ahead Adder.
- Design of 2-to-4 decoder
- Design of 8-to-3 encoder (without and with parity)
- Design of 8-to-1 multiplexer
- Design of 4 bit binary to gray converter
- Design of Multiplexer/ Demultiplexer, comparator
- Design of Full adder using 3 modeling styles
- Design of flip flops: SR, D, JK, T
- Design of 4-bit binary, BCD counters ( synchronous/ asynchronous reset) or any sequence counter
- Design of a N- bit Register of Serial- in Serial –out, Serial in parallel out, Parallel in
- Serial out and Parallel in Parallel Out.
- Design of Sequence Detector (Finite State Machine- Mealy and Moore Machines).
- Design of 4- Bit Multiplier, Divider.
- Design of ALU to Perform – ADD, SUB, AND-OR, 1’s and 2’s Compliment,
- Multiplication, and Division.
- Design of Finite State Machine.
- Implementing the above designs on Xilinx/Altera/Cypress/equivalent based FPGA/CPLD kits
Part –II
- Static and Dynamic Characteristics of CMOS Inverter
- Implementation of EX-OR gate using complementary CMOS, Psedo-NMOS, Dynamic and domino logic style
- Implementation of Full Adder using Transmission Gates
For all other M.Tech 1st Year 1st Sem syllabus go to JNTUH M.Tech VLSI/ VLSI Design/VLSI System Design 1st Year 1st Sem Course Structure for (R17) Batch.
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