{"id":7391,"date":"2019-12-14T16:54:28","date_gmt":"2019-12-14T16:54:28","guid":{"rendered":"https:\/\/www.inspirenignite.com\/vtu\/digital-electronics-telecom-3rd-sem-syllabus-for-vtu-be-2017-scheme\/"},"modified":"2019-12-14T16:54:28","modified_gmt":"2019-12-14T16:54:28","slug":"digital-electronics-telecom-3rd-sem-syllabus-for-vtu-be-2017-scheme","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/vtu\/digital-electronics-telecom-3rd-sem-syllabus-for-vtu-be-2017-scheme\/","title":{"rendered":"Digital Electronics Telecom 3rd Sem Syllabus for VTU BE 2017 Scheme"},"content":{"rendered":"<p>Digital Electronics detail syllabus for Telecommunication Engineering (Telecom), 2017 scheme is taken from <a href=\"https:\/\/vtu.ac.in\/b-e-scheme-syllabus\/\" target=\"_blank\" rel=\"noopener\">VTU<\/a> official website and presented for VTU students. The course code (17EC34), and for exam duration, Teaching Hr\/week, Practical Hr\/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.<\/p>\n<p>For all other telecom 3rd sem syllabus for be 2017 scheme vtu you can visit <a href=\"..\/telecom-3rd-sem-syllabus-for-be-2017-scheme-vtu\">Telecom 3rd Sem syllabus for BE 2017 Scheme VTU Subjects<\/a>. The detail syllabus for digital electronics is as follows.<\/p>\n<p><h4>Course Objectives:<\/h4>\n<p> This course will enable students to:<\/p>\n<ul>\n<li>Illustrate simplification of Algebraic equations using Karnaugh Maps and Quine-McClusky Techniques.<\/li>\n<li>Design combinational logic circuits.<\/li>\n<li>Design Decoders, Encoders, Digital Multiplexer, Adders, Subtractors and Binary Comparators.<\/li>\n<li>Describe Latches and Flip-flops, Registers and Counters.<\/li>\n<li>Analyze Mealy and Moore Models.<\/li>\n<li>Develop state diagrams Synchronous Sequential Circuits.<\/li>\n<\/ul>\n<p><h4>Module 1<br \/>\nFor complete syllabus and results, class timetable and more pls <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">download iStudy<\/a>. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.<\/p>\n<p><h4>Module 2<br \/>\n<\/h4>\n<p>Analysis and design of combinational logic: General approach to combinational logic design, Decoders, BCD decoders, Encoders, digital multiplexers,\tUsing multiplexers as Boolean function generators, Adders and subtractors, Cascading full adders, Look ahead carry, Binary comparators &#8216;Text 1, Chapter 4&#8217;.\n<\/p>\n<p><h4>Module 3<br \/>\n<\/h4>\n<p>Flip-Flops: Basic Bistable elements, Latches, Timing considerations, The master-slave flip-flops (pulse-triggered flip-flops): SR flip-flops, JK flip-flops, Edge triggered flipflops, Characteristic equations. &#8216;Text 2, Chapter 6&#8217;\n<\/p>\n<p><h4>Module 4<br \/>\nFor complete syllabus and results, class timetable and more pls <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">download iStudy<\/a>. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.<\/p>\n<p><h4>Module 5<br \/>\n<\/h4>\n<p>Sequential Circuit Design: Mealy and Moore models, State machine notation, Synchronous Sequential circuit analysis, Construction of state diagrams, counter design. &#8216;Text 1, Chapter 6&#8217;\n<\/p>\n<p><h4>Course Outcomes:<\/h4>\n<p> After studying this course, students will be able to:<\/p>\n<ul>\n<li>Develop simplified switching equation using Karnaugh Maps and Quine-McClusky techniques.<\/li>\n<li>Explain the operation of decoders, encoders, multiplexers, demultiplexers, adders, subtractors and comparators.<\/li>\n<li>Explain the working of Latches and Flip Flops (SR,D,T and JK).<\/li>\n<li>Design Synchronous\/Asynchronous Counters and Shift registers using Flip Flops.<\/li>\n<li>Develop Mealy\/Moore Models and state diagrams for the given clocked sequential circuits.<\/li>\n<li>Apply the knowledge gained in the design of Counters and Registers.<\/li>\n<\/ul>\n<p><h4>Text Books:<br \/>\n<\/h4>\n<ol>\n<li>Digital Logic Applications and Design, John M Yarbrough, Thomson Learning, 2001. ISBN 981-240-062-1.<\/li>\n<li>Donald D. Givone, Digital Principles and Design, McGraw Hill, 2002. ISBN 978-007-052906-9.<\/li>\n<\/ol>\n<p><h4>Reference Books:<\/h4>\n<ol>\n<li>D. P. Kothari and J. S Dhillon, Digital Circuits and Design, Pearson, 2016, ISBN:9789332543539.<\/li>\n<li>Morris Mano, Digital Design, Prentice Hall of India, Third Edition.<\/li>\n<li>Charles H Roth, Jr., Fundamentals of logic design, Cengage Learning.<\/li>\n<li>K. A. Navas, Electronics Lab Manual, Volume I, PHI, 5th Edition, 2015, ISBN: 9788120351424.<\/li>\n<\/li>\n<\/ol>\n<p>For detail syllabus of all other subjects of BE Telecom, 2017 scheme do visit <a href=\"..\/category\/telecom+3rd-sem\">Telecom 3rd Sem syllabus for 2017 scheme<\/a>.<\/p>\n<p>Dont forget to <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">download iStudy<\/a> for latest syllabus and results, class timetable and more.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Digital Electronics detail syllabus for Telecommunication Engineering (Telecom), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17EC34), and for exam duration, Teaching [&hellip;]<\/p>\n","protected":false},"author":2298,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[4,47],"tags":[],"class_list":["post-7391","post","type-post","status-publish","format-standard","hentry","category-3rd-sem","category-telecom"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/7391","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/users\/2298"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/comments?post=7391"}],"version-history":[{"count":0,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/7391\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/media?parent=7391"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/categories?post=7391"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/tags?post=7391"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}