{"id":7272,"date":"2019-12-14T16:52:56","date_gmt":"2019-12-14T16:52:56","guid":{"rendered":"https:\/\/www.inspirenignite.com\/vtu\/digital-system-design-nano-5th-sem-syllabus-for-vtu-be-2017-scheme\/"},"modified":"2019-12-14T16:52:56","modified_gmt":"2019-12-14T16:52:56","slug":"digital-system-design-nano-5th-sem-syllabus-for-vtu-be-2017-scheme","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/vtu\/digital-system-design-nano-5th-sem-syllabus-for-vtu-be-2017-scheme\/","title":{"rendered":"Digital System Design Nano 5th Sem Syllabus for VTU BE 2017 Scheme"},"content":{"rendered":"

Digital System Design detail syllabus for Nanoelectronics (Nano), 2017 scheme is taken from VTU<\/a> official website and presented for VTU students. The course code (17NT54), and for exam duration, Teaching Hr\/week, Practical Hr\/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.<\/p>\n

For all other nano 5th sem syllabus for be 2017 scheme vtu you can visit Nano 5th Sem syllabus for BE 2017 Scheme VTU Subjects<\/a>. The detail syllabus for digital system design is as follows.<\/p>\n

Course Objectives:<\/h4>\n
    \n
  1. To design sub systems using combinational circuits and sequential circu<\/li>\n
  2. To design digital systems using CMOS logic and understand the phys digital systems in its transistor schematic form<\/li>\n
  3. To learn Verilog HDL programming and model digital systems using hig\t\t\t\tits ical structure of h level language<\/li>\n<\/ol>\n

    Module 1:<\/h4>\n

    For complete syllabus and results, class timetable and more pls download iStudy<\/a>. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.<\/p>\n

    Module 2:<\/h4>\n

    DESIGNING WITH COMBINATIONAL CIRCUITS: 4-bit Ripple carry adder, 4-bit carry look ahead adder, 4-bit carry select adder, 4-bit comparator using 2-bit comparator, seven segment display controllers using encoders and decoders, parity generators and 3-bit shifters\/rotators using multiplexers, barrel shifter\/rotator using 2:1 multiplexer Writing Verilog code for 4-bit ripple carry adder, parity generators.\t\t10\n<\/p>\n

    Module 3:<\/h4>\n

    DESIGNING WITH SEQUENTIAL CIRCUITS: SR latch, SR-D Latch, T-Latch, flip flops using positive triggered and negative triggered latch, designing N-bit synchronous and asynchronous counters, up-down counters, designing clock dividers using counters, shift registers, SISO, SIPO, PISO, PIPO, 1-bit memory unit with read and write enable, 4-bit memory unit with address decoder.\t\t10\n<\/p>\n

    Module 4:<\/h4>\n

    For complete syllabus and results, class timetable and more pls download iStudy<\/a>. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.<\/p>\n

    Module 5:<\/h4>\n

    SUBSYSTEM DESIGN AND MODELLING: writing Verilog code using data flow description for D-latch, JK-flip flop, counters, 2-Bit Magnitude comparators, 4×4 memory with read and write ports, behavioural model for 4-bit ALU design using Verilog HDL, writing test bench wave forms for functional verification of 4-bit adders and ALU Introduction to programmable logics such as PLA, PAL and FPGAs\t10\n<\/p>\n

    Course Outcomes:<\/h4>\n

    After successfully completing this course, students will be able to understand:<\/p>\n