{"id":7164,"date":"2019-12-14T16:51:49","date_gmt":"2019-12-14T16:51:49","guid":{"rendered":"https:\/\/www.inspirenignite.com\/vtu\/digital-design-and-hdl-med-elec-3rd-sem-syllabus-for-vtu-be-2017-scheme\/"},"modified":"2019-12-14T16:51:49","modified_gmt":"2019-12-14T16:51:49","slug":"digital-design-and-hdl-med-elec-3rd-sem-syllabus-for-vtu-be-2017-scheme","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/vtu\/digital-design-and-hdl-med-elec-3rd-sem-syllabus-for-vtu-be-2017-scheme\/","title":{"rendered":"Digital Design and Hdl Med Elec 3rd Sem Syllabus for VTU BE 2017 Scheme"},"content":{"rendered":"<p>Digital Design and Hdl detail syllabus for Medical Electronics (Med Elec), 2017 scheme is taken from <a href=\"https:\/\/vtu.ac.in\/b-e-scheme-syllabus\/\" target=\"_blank\" rel=\"noopener\">VTU<\/a> official website and presented for VTU students. The course code (17ML34), and for exam duration, Teaching Hr\/week, Practical Hr\/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.<\/p>\n<p>For all other med elec 3rd sem syllabus for be 2017 scheme vtu you can visit <a href=\"..\/med-elec-3rd-sem-syllabus-for-be-2017-scheme-vtu\">Med Elec 3rd Sem syllabus for BE 2017 Scheme VTU Subjects<\/a>. The detail syllabus for digital design and hdl is as follows.<\/p>\n<p><h4>Course Objectives:<\/h4>\n<p> This course will enable the students to<\/p>\n<ul>\n<li>To impart the concepts of simplifying Boolean expression using K-map techniques and provide an understanding of logic families<\/li>\n<li>To impart the concepts of designing and analyzing combinational logic circuits<\/li>\n<li>To provide an understanding for the concepts of HDL-Verilog, data flow and behavioral models for the design of digital systems.<\/li>\n<li>To impart design methods and analysis of sequential logic circuits<\/li>\n<\/ul>\n<p><h4>Module 1<\/h4>\n<p>For complete syllabus and results, class timetable and more pls <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">download iStudy<\/a>. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.<\/p>\n<p><h4>Module 2<\/h4>\n<p>Combinational Functions: Arithmetic Operations: Adders and subtractors-cascading full adders, Look ahead carry, Binary Comparators &#8211; 2 bit and 4 bit, two bit Multiplier, Verilog Description of for above circuits. Multiplexers-Realization of 2:1, 4:1 and 8:1 using gates &amp; Applications. Demultiplexers: -Realization of 1:2 1:4 and 1:8 using basic gates &amp; Applications Verilog Behavioral description: Structure, variable assignment statement, sequential statements, loop statements, Verilog behavioral description of Multiplexers (2:1,4:1,8:1) and De-multiplexers (1:2,1:4,1:8.\n<\/p>\n<p><h4>Module 3 <\/h4>\n<p>Analysis and design of combinational logic: Encoders: Binary coded decimal codes, Binary &#8211; Gray vice versa, BCD &#8211; Excess 3 Encoders: Realization and Priority Encoders, Decoders: BCD &#8211; Decimal, BCD &#8211; Seven segment, Seven segment display. Verilog behavioral description of Encoders (8 to 3 with priority and without priority), Decoders (2 to 4).\n<\/p>\n<p><h4>Module 4<\/h4>\n<p>For complete syllabus and results, class timetable and more pls <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">download iStudy<\/a>. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.<\/p>\n<p><h4>Module 5<\/h4>\n<p>Counters, design and their applications: Counters-Binary ripple counters, Synchronous binary counters, Modulo N counters &#8211; Synchronous and Asynchronous counters. Verilog behavioral description of Synchronous and Asynchronous counters, sequential counters. Synthesis of Verilog: Mapping process in the hardware domain- Mapping of signal assignment, variable assignment, if statements, else-if statements, loop statements\n<\/p>\n<p><h4>Course Outcomes:<\/h4>\n<p> After studying this course, students will able to:<\/p>\n<ul>\n<li>Simplify Boolean functions using K-map and Quine-McCluskey minimization technique<\/li>\n<li>Analyze, design and write verilog code for combinational logic circuits. (MUX, De-MUX, adder and subtractor, and comparator circuits)<\/li>\n<li>Analyze and design code converters, encoders and decoders.<\/li>\n<li>Analyze and design of synchronous sequential circuits<\/li>\n<li>Analyze sequential circuits, Moore\/Mealy machines<\/li>\n<\/ul>\n<p><h4>Graduate Attributes (as per NBA):<\/h4>\n<ul>\n<li>Engineering knowledge<\/li>\n<li>Problem analysis<\/li>\n<li>Design &amp; Development of Solutions<\/li>\n<li>Modern tool usage<\/li>\n<\/ul>\n<p><h4>Question paper pattern:<\/h4>\n<ul>\n<li>The question paper will have TEN questions.<\/li>\n<li>Each full question consists of 16 marks.<\/li>\n<li>There will be 2 full questions (with maximum of THREE sub questions) from each module.<\/li>\n<li>Each full question will have sub questions covering all the topics under a module.<\/li>\n<li>The students will have to answer 5 full questions, selecting one full question from each module.<\/li>\n<\/ul>\n<p><h4>Text Books:<\/h4>\n<ol>\n<li>Digital Logic Applications and Design by John M Yarbrough, Thomson Learning,2001 (Modules 1,2,3,4,5 -Logic design)<\/li>\n<li>HDL Programming VHDL and Verilog by Nazeih M. Botros, 2009 reprint, Dreamtech press.(Modules 1,2,3,4,5 Verilog description.<\/li>\n<\/ol>\n<p><h4>Reference Books:<\/h4>\n<ol>\n<li>Charles H Roth, Jr., Fundamentals of logic design, Cengage Learning<\/li>\n<li>Digital Principals and Design &#8211; Donald D Givone,12th reprint, TMH,2008<\/li>\n<li>Logic Design, Sudhakar Samuel, Pearson\/ Saguine, 2007<\/li>\n<li>Fundamentals of HDL- Cyril P R Pearson\/Sanguin 2010.<\/li>\n<\/li>\n<\/ol>\n<p>For detail syllabus of all other subjects of BE Med Elec, 2017 scheme do visit <a href=\"..\/category\/med-elec+3rd-sem\">Med Elec 3rd Sem syllabus for 2017 scheme<\/a>.<\/p>\n<p>Dont forget to <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">download iStudy<\/a> for latest syllabus and results, class timetable and more.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Digital Design and Hdl detail syllabus for Medical Electronics (Med Elec), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17ML34), and for [&hellip;]<\/p>\n","protected":false},"author":2298,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[4,42],"tags":[],"class_list":["post-7164","post","type-post","status-publish","format-standard","hentry","category-3rd-sem","category-med-elec"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/7164","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/users\/2298"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/comments?post=7164"}],"version-history":[{"count":0,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/7164\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/media?parent=7164"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/categories?post=7164"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/tags?post=7164"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}