{"id":6940,"date":"2019-12-14T16:48:35","date_gmt":"2019-12-14T16:48:35","guid":{"rendered":"https:\/\/www.inspirenignite.com\/vtu\/digital-system-design-eee-3rd-sem-syllabus-for-vtu-be-2017-scheme\/"},"modified":"2019-12-14T16:48:35","modified_gmt":"2019-12-14T16:48:35","slug":"digital-system-design-eee-3rd-sem-syllabus-for-vtu-be-2017-scheme","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/vtu\/digital-system-design-eee-3rd-sem-syllabus-for-vtu-be-2017-scheme\/","title":{"rendered":"Digital System Design EEE 3rd Sem Syllabus for VTU BE 2017 Scheme"},"content":{"rendered":"<p>Digital System Design detail syllabus for Electrical Engineering (Eee), 2017 scheme is taken from <a href=\"https:\/\/vtu.ac.in\/b-e-scheme-syllabus\/\" target=\"_blank\" rel=\"noopener\">VTU<\/a> official website and presented for VTU students. The course code (17EE35), and for exam duration, Teaching Hr\/week, Practical Hr\/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.<\/p>\n<p>For all other eee 3rd sem syllabus for be 2017 scheme vtu you can visit <a href=\"..\/eee-3rd-sem-syllabus-for-be-2017-scheme-vtu\">EEE 3rd Sem syllabus for BE 2017 Scheme VTU Subjects<\/a>. The detail syllabus for digital system design is as follows.<\/p>\n<p><h4>Course Objectives:<\/h4>\n<ul>\n<li>To impart the knowledge of combinational circuit design.<\/li>\n<li>To impart the knowledge of Sequential circuit design.<\/li>\n<li>To provide the basic knowledge about VHDL &amp; its use<\/li>\n<\/ul>\n<p><h4>Module 1\t\t\t\t\t\t<\/h4>\n<p>For complete syllabus and results, class timetable and more pls <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">download iStudy<\/a>. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.<\/p>\n<p><h4>Module 2<\/h4>\n<p>Analysis and design of Combinational Logic: General approach, Decoders-BCD decoders, Encoders. Digital multiplexers-using multiplexers as Boolean function generators. Adders and Subtractors-Cascading full adders, Look ahead carry, Binary comparators. Design methods of building blocks of combinational logics\n<\/p>\n<p><h4>Module 3<\/h4>\n<p>Sequential Circuits: Basic Bistable element, Latches, SR latch, application of SR latch, A Switch debouncer, The gated SR latch. The gated D Latch, The Master-Slave Flip-Flops (Pulse-Triggered Flip-Flops): The master-slave SR Flip-Flops, The master-slave JK Flip-Flop. Characteristic equations, Registers, Counters-Binary Ripple Counter, Synchronous Binary counters, Counters based on Shift Registers, Design of a Synchronous counters, Design of a Synchronous Mod-6 counters using clocked JK Flip-Flops Design of a Synchronous Mod-6 counter using clocked D, T, or SR FlipFlops\n<\/p>\n<p><h4>Module 4<\/h4>\n<p>For complete syllabus and results, class timetable and more pls <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">download iStudy<\/a>. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.<\/p>\n<p><h4>Module 5<\/h4>\n<p>HDL: Introduction, A brief history of HDL, Structure of HDL Module, Operators, Data types, Types of Descriptions (only VHDL), Simulation and synthesis, Brief comparison of VHDL and Verilog. Data-Flow Descriptions: Highlights of Data flow descriptions, Structure of data-flow description,\n<\/p>\n<p><h4>Course Outcomes:<\/h4>\n<p>At the end of the course the student will be able to:<\/p>\n<ul>\n<li>Simplify switching equations generated from truth tables.<\/li>\n<li>Design combinational logic circuits; adders, Subtractors and comparators.<\/li>\n<li>Design synchronous sequential circuits; latches, flip-flops, binary counters and Mod &#8211;<\/li>\n<li>Design Mealy and Moore synchronous sequential circuit models.<\/li>\n<li>Construct state diagrams for sequential circuits.<\/li>\n<li>Describe the structure of HDL module, operators,data types.<\/li>\n<li>Give Comparison between VHDL and Verilog.<\/li>\n<li>Understand the concept of data-flow description\t\t\t6 counters.<\/li>\n<\/ul>\n<p><h4>Graduate Attributes (as per NBA):<\/h4>\n<ul>\n<li>Engineering Knowledge,<\/li>\n<li>Problem Analysis,<\/li>\n<li>Life-Long Learning,<\/li>\n<li>Accomplishment of Complex Problems<\/li>\n<\/ul>\n<p><h4>Question paper pattern:<\/h4>\n<ul>\n<li>The question paper will have ten questions.<\/li>\n<li>Each full question is for 16 marks.<\/li>\n<li>There will be 2full questions (with a maximum of four sub questions in one full question) from each module.<\/li>\n<li>Each full question with sub questions will cover the contents under a module.<\/li>\n<li>Students will have to answer 5 full questions, selecting one full question from each module<\/li>\n<\/ul>\n<p><h4>Text Books:<\/h4>\n<ol>\n<li>Digital Logic Applications and\tJohn M Yarbrough\tCengageLearn\t2011<\/li>\n<li>Digital Principles and Design\tDonald D Givone\tMcGraw Hill\t1st Edition, 2002<\/li>\n<\/ol>\n<p><h4>Reference Books:<\/h4>\n<ol>\n<li>Logic and computer design Fundamentals\tM. Morries Mano and Charles Kime\tPearson Learning\t4th Edition, 2014<\/li>\n<li>Fundamentals of logic design\tCharles H Roth, JR and Larry L. Kinney\tCengage Learning\t6th Edition, 2013<\/li>\n<li>Fundamentals of Digital Circuits\tA. Anand Kumar\tPHI\t3rd Edition, 2014<\/li>\n<li>Digital Logic Design and VHDL\tA.A.Phadke, S.M.Deokar\tWiley India\t1st Edition, 2009<\/li>\n<li>Digital Circuits and Design\tD.P. KothariJ. S.Dhillon\tPearson\tFirst Print 2015<\/li>\n<li>HDL Programming (VHDL and Verilog. Nazeih M. Botros\tCengage Learning\t1st Edition, 2011<\/li>\n<li>Circuit Design and Simulation with VHDL\tVolnei A Pedroni\tPHI\t2nd Edition,<\/li>\n<\/li>\n<\/ol>\n<p>For detail syllabus of all other subjects of BE Eee, 2017 scheme do visit <a href=\"..\/category\/eee+3rd-sem\">Eee 3rd Sem syllabus for 2017 scheme<\/a>.<\/p>\n<p>Dont forget to <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">download iStudy<\/a> for latest syllabus and results, class timetable and more.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Digital System Design detail syllabus for Electrical Engineering (Eee), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17EE35), and for exam duration, [&hellip;]<\/p>\n","protected":false},"author":2298,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[4,8],"tags":[],"class_list":["post-6940","post","type-post","status-publish","format-standard","hentry","category-3rd-sem","category-eee"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/6940","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/users\/2298"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/comments?post=6940"}],"version-history":[{"count":0,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/6940\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/media?parent=6940"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/categories?post=6940"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/tags?post=6940"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}