{"id":6927,"date":"2019-12-14T16:48:28","date_gmt":"2019-12-14T16:48:28","guid":{"rendered":"https:\/\/www.inspirenignite.com\/vtu\/vlsi-lab-ece-7th-sem-syllabus-for-vtu-be-2017-scheme\/"},"modified":"2019-12-14T16:48:28","modified_gmt":"2019-12-14T16:48:28","slug":"vlsi-lab-ece-7th-sem-syllabus-for-vtu-be-2017-scheme","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/vtu\/vlsi-lab-ece-7th-sem-syllabus-for-vtu-be-2017-scheme\/","title":{"rendered":"Vlsi Lab ECE 7th Sem Syllabus for VTU BE 2017 Scheme"},"content":{"rendered":"<p>Vlsi Lab detail syllabus for Electronics &amp; Communication Engineering (Ece), 2017 scheme is taken from <a href=\"https:\/\/vtu.ac.in\/b-e-scheme-syllabus\/\" target=\"_blank\" rel=\"noopener\">VTU<\/a> official website and presented for VTU students. The course code (17ECL77), and for exam duration, Teaching Hr\/week, Practical Hr\/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.<\/p>\n<p>For all other ece 7th sem syllabus for be 2017 scheme vtu you can visit <a href=\"..\/ece-7th-sem-syllabus-for-be-2017-scheme-vtu\">ECE 7th Sem syllabus for BE 2017 Scheme VTU Subjects<\/a>. The detail syllabus for vlsi lab is as follows.<\/p>\n<p><h4>Course Objectives:<\/h4>\n<p> This course will enable students to:<\/p>\n<ul>\n<li>Explore the CAD tool and understand the flow of the Full Custom IC design cycle.<\/li>\n<li>Learn DRC, LVS and Parasitic Extraction of the various designs.<\/li>\n<li>Design and simulate the various basic CMOS analog circuits and use them in higher circuits like data converters using design abstraction concepts.<\/li>\n<li>Design and simulate the various basic CMOS digital circuits and use them in higher circuits like adders and shift registers using design abstraction concepts.<\/li>\n<p>Experiments can be conducted using any of the following or equivalent design tools: Cadence\/Synopsis\/Mentor Graphics\/Microwind\n<\/ul>\n<\/p>\n<p><h4>Laboratory Experiments:<\/h4>\n<p>For complete syllabus and results, class timetable and more pls <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">download iStudy<\/a>. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.<\/p>\n<p><h4>Part &#8211; A:<\/h4>\n<p> ASIC-DIGITAL DESIGN\t\t\t<\/p>\n<ol>\n<li>Write Verilog Code for the following circuits and their Test Bench for verification, o[SAR]<\/li>\n<\/ol>\n<p><h4>Part &#8211; B:<\/h4>\n<p> ANALOG DESIGN<\/p>\n<ol>\n<li>Design an Inverter with given specifications**, completing the design flow mentioned below:<\/li>\n<ol type=\"a\">\n<li>Draw the schematic and verify the following<\/li>\n<ol type=\"i\">\n<li>DC Analysis<\/li>\n<li>Transient Analysis<\/li>\n<\/ol>\n<li>Draw the Layout and verify the DRC, ERC<\/li>\n<li>Check for LVS<\/li>\n<li>Extract RC and back annotate the same and verify the Design<\/li>\n<li>Verify &amp; Optimize for Time, Power and Area to the given constraint*<\/li>\n<\/ol>\n<li>Design the<\/li>\n<ol type=\"i\">\n<li>Common source and Common Drain amplifier and<\/li>\n<li>A Single Stage differential amplifier, with given specifications**, completing the<\/li>\n<p>design flow mentioned below:<\/p>\n<ol type=\"a\">\n<li>Draw the schematic and verify the following<\/li>\n<li>DC Analysis<\/li>\n<li>AC Analysis<\/li>\n<li>Transient Analysis<\/li>\n<\/ol>\n<li>Draw the Layout and verify the DRC, ERC<\/li>\n<li>Check for LVS<\/li>\n<li>Extract RC and back annotate the same and verify the Design.<\/li>\n<\/ol>\n<li>Design an op-amp with given specification** using given differential amplifier Common source and Common Drain amplifier in library*** and completing the design flow mentioned below:<\/li>\n<ol type=\"a\">\n<li>Draw the schematic and verify the following<\/li>\n<ol type=\"i\">\n<li>DC Analysis<\/li>\n<li>. AC Analysis<\/li>\n<li>Transient Analysis<\/li>\n<\/ol>\n<li>Draw the Layout and verify the DRC, ERC<\/li>\n<li>Check for LVS<\/li>\n<li>Extract RC and back annotate the same and verify the Design.<\/li>\n<\/ol>\n<li>Design a 4 bit R-2R based DAC for the given specification and completing the<\/li>\n<p>design flow mentioned using given op-amp in the library***.<\/p>\n<ol type=\"a\">\n<li>Draw the schematic and verify the following<\/li>\n<ol type=\"i\">\n<li>DC Analysis<\/li>\n<li>AC Analysis<\/li>\n<li>Transient Analysis<\/li>\n<\/ol>\n<li>Draw the Layout and verify the DRC, ERC<\/li>\n<\/ol>\n<li>For the SAR based ADC mentioned in the figure below draw the mixed signal schematic and verify the functionality by completing ASIC Design FLOW.<\/li>\n<p>*<br \/>\nAn appropriate constraint should be given.<br \/>\n** Appropriate specification should be given.<br \/>\n*** Applicable Library should be added &amp; information should be given to the Designer.\n<\/ol>\n<\/p>\n<p><h4>Course Outcomes:<\/h4>\n<p>For complete syllabus and results, class timetable and more pls <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">download iStudy<\/a>. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.<\/p>\n<p><h4>Conduct of Practical Examinations:<\/h4>\n<ul>\n<li>All practicals are to be included for practical examination.<\/li>\n<li>For examination, one question from PART.A and one question from PART.B to be set.<\/li>\n<li>Students are allowed to pick one experiment from the lot.<\/li>\n<li>Change of experiment is allowed only once and Marks allotted to the procedure part to be made zero.<\/li>\n<\/li>\n<\/ul>\n<p>For detail syllabus of all other subjects of BE Ece, 2017 scheme do visit <a href=\"..\/category\/ece+7th-sem\">Ece 7th Sem syllabus for 2017 scheme<\/a>.<\/p>\n<p>Dont forget to <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">download iStudy<\/a> for latest syllabus and results, class timetable and more.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Vlsi Lab detail syllabus for Electronics &amp; Communication Engineering (Ece), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17ECL77), and for exam [&hellip;]<\/p>\n","protected":false},"author":2298,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[20,7],"tags":[],"class_list":["post-6927","post","type-post","status-publish","format-standard","hentry","category-7th-sem","category-ece"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/6927","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/users\/2298"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/comments?post=6927"}],"version-history":[{"count":0,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/6927\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/media?parent=6927"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/categories?post=6927"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/tags?post=6927"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}