{"id":6914,"date":"2019-12-14T16:48:21","date_gmt":"2019-12-14T16:48:21","guid":{"rendered":"https:\/\/www.inspirenignite.com\/vtu\/hdl-lab-ece-5th-sem-syllabus-for-vtu-be-2017-scheme\/"},"modified":"2019-12-14T16:48:21","modified_gmt":"2019-12-14T16:48:21","slug":"hdl-lab-ece-5th-sem-syllabus-for-vtu-be-2017-scheme","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/vtu\/hdl-lab-ece-5th-sem-syllabus-for-vtu-be-2017-scheme\/","title":{"rendered":"Hdl Lab ECE 5th Sem Syllabus for VTU BE 2017 Scheme"},"content":{"rendered":"<p>Hdl Lab detail syllabus for Electronics &amp; Communication Engineering (Ece), 2017 scheme is taken from <a href=\"https:\/\/vtu.ac.in\/b-e-scheme-syllabus\/\" target=\"_blank\" rel=\"noopener\">VTU<\/a> official website and presented for VTU students. The course code (17ECL58), and for exam duration, Teaching Hr\/week, Practical Hr\/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.<\/p>\n<p>For all other ece 5th sem syllabus for be 2017 scheme vtu you can visit <a href=\"..\/ece-5th-sem-syllabus-for-be-2017-scheme-vtu\">ECE 5th Sem syllabus for BE 2017 Scheme VTU Subjects<\/a>. The detail syllabus for hdl lab is as follows.<\/p>\n<p><h4>Course Objectives:<\/h4>\n<p> This course will enable students to:<\/p>\n<ul>\n<li>Familiarize with the CAD tool to write HDL programs.<\/li>\n<li>Understand simulation and synthesis of digital design.<\/li>\n<li>Program FPGAs\/CPLDs to synthesize the digital designs.<\/li>\n<li>Interface hardware to programmable ICs through I\/O ports.<\/li>\n<li>Choose either Verilog or VHDL for a given Abstraction level.<\/li>\n<p>Note: Programming can be done using any compiler. Download the programs on a FPGA\/CPLD boards such as Apex\/Acex\/Max\/Spart.an\/Sinfi or equivalent and performance testing may be done using 32 channel pattern generator and logic analyzer apart from verification by simulation with tools such as Altera\/Modelsim or equivalent.\n<\/ul>\n<\/p>\n<p><h4>Laboratory Experiments:<\/h4>\n<p>For complete syllabus and results, class timetable and more pls <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">download iStudy<\/a>. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.<\/p>\n<p><h4>Part &#8211; A:<\/h4>\n<p> PROGRAMMING<\/p>\n<ol>\n<li>Write Verilog code to realize all the logic gates<\/li>\n<li>Write a Verilog program for the following combinational designs<\/li>\n<ol type=\"a\">\n<li>2 to 4 decoder<\/li>\n<li>8 to 3 (encoder without priority &amp; with priority)<\/li>\n<li>8 to 1 multiplexer.<\/li>\n<li>4 bit binary to gray converter<\/li>\n<li>Multiplexer, de-multiplexer, comparator.<\/li>\n<\/ol>\n<li>Write a VHDL and Verilog code to describe the functions of a Full Adder using three modeling styles.<\/li>\n<li>Write a Verilog code to model 32 bit ALU using the schematic diagram shown below<\/li>\n<p>A (31:0. B(31:0)<br \/>\nOpcode (3:0)<br \/>\nOutput<br \/>\nEnable<\/p>\n<ul>\n<li>ALU should use combinational logic to calculate an output based on the four bit op-code input.<\/li>\n<li>ALU should pass the result to the out bus when enable line in high, and tri-state the out bus when the enable line is low.<\/li>\n<li>ALU should decode the 4 bit op-code according to the example given below.<\/li>\n<p>OPCODE\tALU Operation\n<\/ul>\n<li>A+B<\/li>\n<li>A-B<\/li>\n<li>A Complement<\/li>\n<li>A*B<\/li>\n<li>A AND B<\/li>\n<li>A OR B<\/li>\n<li>A NAND B<\/li>\n<li>A XOR B<\/li>\n<li>Develop the Verilog code for the following flip-flops, SR, D, JK and T.<\/li>\n<li>Design a 4 bit binary, BCD counters (Synchronous reset and Asynchronous reset) and any sequence counters, using Verilog code.<\/li>\n<\/ol>\n<p><h4>Part &#8211; B:<\/h4>\n<p> INTERFACING (at least four of the following must be covered using VHDL\/Verilog)<\/p>\n<ol>\n<li>Write HDL code to display messages on an alpha numeric LCD display.<\/li>\n<li>Write HDL code to interface Hex key pad and display the key code on seven segment display.<\/li>\n<li>Write HDL code to control speed, direction of DC and Stepper motor.<\/li>\n<li>Write HDL code to accept Analog signal, Temperature sensor and display the data on LCD or Seven segment display.<\/li>\n<li>Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp etc.,) using DAC &#8211; change the frequency.<\/li>\n<li>Write HDL code to simulate Elevator operation.<\/li>\n<\/ol>\n<p><h4>Course Outcomes:<\/h4>\n<p>For complete syllabus and results, class timetable and more pls <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">download iStudy<\/a>. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.<\/p>\n<p><h4>Conduct of Practical Examinations:<\/h4>\n<ol>\n<li>All practicals are to be included for practical examination.<\/li>\n<li>Strictly follow the instructions as printed on the cover page of answer script for breakup of marks.<\/li>\n<li>Change of experiment is allowed only once and Marks allotted to the procedure part to be made zero.<\/li>\n<\/li>\n<\/ol>\n<p>For detail syllabus of all other subjects of BE Ece, 2017 scheme do visit <a href=\"..\/category\/ece+5th-sem\">Ece 5th Sem syllabus for 2017 scheme<\/a>.<\/p>\n<p>Dont forget to <a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">download iStudy<\/a> for latest syllabus and results, class timetable and more.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Hdl Lab detail syllabus for Electronics &amp; Communication Engineering (Ece), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17ECL58), and for exam [&hellip;]<\/p>\n","protected":false},"author":2298,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[18,7],"tags":[],"class_list":["post-6914","post","type-post","status-publish","format-standard","hentry","category-5th-sem","category-ece"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/6914","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/users\/2298"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/comments?post=6914"}],"version-history":[{"count":0,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/6914\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/media?parent=6914"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/categories?post=6914"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/tags?post=6914"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}