{"id":561,"date":"2016-09-09T13:51:37","date_gmt":"2016-09-09T13:51:37","guid":{"rendered":"http:\/\/www.inspirenignite.com\/vtu\/?p=561"},"modified":"2019-08-31T14:53:38","modified_gmt":"2019-08-31T14:53:38","slug":"digital-design-hdl-syllabus-vtu-beb-tech","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/vtu\/digital-design-hdl-syllabus-vtu-beb-tech\/","title":{"rendered":"Digital Design and HDL Syllabus for VTU BE\/B.Tech CBCS 2015-16"},"content":{"rendered":"<p>Digital Design and HDL Syllabus for VTU BE\/B.Tech Biomedical Engineering third sem complete syllabus covered here. This will help you understand complete curriculum along with details such as exam marks and duration. The details are as follows.<\/p>\n<table>\n<tbody>\n<tr>\n<th>Subject Code<\/th>\n<th>\u00a015 EI\/BM\/ML 34<\/th>\n<th>IA Marks<\/th>\n<th>20<\/th>\n<\/tr>\n<tr>\n<td>Number of Lecture Hours\/Week<\/td>\n<td>04<\/td>\n<td>Exam Marks<\/td>\n<td>80<\/td>\n<\/tr>\n<tr>\n<td>Total Number of Lecture Hours<\/td>\n<td>50<\/td>\n<td>Exam Hours<\/td>\n<td>3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>CREDITS \u2013 04<\/strong><\/p>\n<p><strong>Course Objectives:<\/strong> This course will enable the students to<\/p>\n<ul>\n<li>To impart the concepts of simplifying Boolean expression using K-map techniques and provide an understanding of logic families<\/li>\n<li>To impart the concepts of designing and analyzing combinational logic circuits<\/li>\n<li>To provide an understanding for the concepts of HDL-Verilog, data flow and behavioral models for the design of digital systems.<\/li>\n<li>To impart design methods and analysis of sequential logic circuits<\/li>\n<\/ul>\n<table>\n<tbody>\n<tr>\n<th>MODULES<\/th>\n<th>TEACHING HOURS<\/th>\n<th>REVISED BLOOM\u2019S TAXONOMY (RBT) LEVEL<\/th>\n<\/tr>\n<tr>\n<td><strong>Module -1 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\u00a0<\/strong><\/td>\n<td>_<\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td><strong>Principles of combinational logic:<\/strong> Definition of combinational logic, Canonical forms, Generation of switching equations from truth tables, Karnaugh maps- up to 4 variables, Quine-McCluskey minimization technique<\/p>\n<p><strong>Introduction to Verilog<\/strong>: Structure of Verilog module, Operators, data types, Styles of description- Data flow description, Behavioral description, Implement logic gates, half adder and full adder using Verilog data flow description.<\/td>\n<td>10 Hours<\/td>\n<td>L2,L3,L4<\/td>\n<\/tr>\n<tr>\n<td><strong>Module -2<\/strong><\/td>\n<td>_<\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td><strong>Combinational Functions<\/strong>:<\/p>\n<p style=\"text-align: center\"><a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\"><strong>Download iStudy App (No Ads, No PDFs) for complete VTU syllabus, results, timetables and all other updates.<\/strong><\/a><\/p>\n<\/td>\n<td>10 Hours<\/td>\n<td>L1,L2,L3<\/td>\n<\/tr>\n<tr>\n<td><strong>Module -3<\/strong><\/td>\n<td><strong>_<\/strong><\/td>\n<td><strong>\u00a0<\/strong><\/td>\n<\/tr>\n<tr>\n<td><strong>Analysis and design of combinational logic<\/strong>: Encoders: Binary coded decimal codes, Binary \u2013 Gray vice versa, BCD \u2013 Excess 3 Encoders: Realization and Priority Encoders, Decoders: BCD \u2013 Decimal, BCD \u2013 Seven segment, Seven segment display.<\/p>\n<p><strong>Verilog behavioral<\/strong> description of Encoders (8 to 3 with priority and without\u00a0priority), Decoders (2 to 4).<\/td>\n<td>10 Hours<\/td>\n<td>L1,L2<\/td>\n<\/tr>\n<tr>\n<td><strong>Module -4<\/strong><\/td>\n<td>_<\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td><strong>Sequential Logic Circuits-<\/strong>1:Latches and Flip-Flops: SR-latch, D-latch, D flip-flop, JK flip-flop, T flip- flop Master slave FF, Edge trigger and Pulse trigger FF , Registers and Shift Registers: PISO, PIPO, SISO,SIPO, Right shift and left shift, Universal Shift register.<\/p>\n<p><strong>Verilog behavioral<\/strong> description of latches (D-latch, SR latch) and flip-flops (D, T, JK, SR flip-flops).<\/td>\n<td>10 Hours<\/td>\n<td>L2,L3,L6<\/td>\n<\/tr>\n<tr>\n<td><strong>Module -5<\/strong><\/td>\n<td>_<\/td>\n<td><\/td>\n<\/tr>\n<tr>\n<td><strong>Counters, design and their applications:<\/strong> Counters-Binary ripple counters, Synchronous binary counters, Modulo N counters \u2013 Synchronous and Asynchronous counters.<\/p>\n<p><strong>Verilog behavioral description<\/strong> of Synchronous and Asynchronous counters, sequential counters.<\/p>\n<p><strong>Synthesis of Verilog<\/strong>: Mapping process in the hardware domain- Mapping of signal assignment, variable assignment, if statements, else-if statements, loop statements<\/td>\n<td>10 Hours<\/td>\n<td>L2,L3,L4,L 6<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>Revised Bloom\u2019s Taxonomy Levels<\/strong>: L1 \u2013 Remembering, L2 \u2013 Understanding, L3 \u2013 Applying, L4 \u2013 Analysing, L5 \u2013 Evaluating, and L6 &#8211; Creating<\/p>\n<p><strong>Course Outcomes:<\/strong> After studying this course, students will able to:<\/p>\n<ul>\n<li>Simplify Boolean functions using K-map and Quine-McCluskey minimization technique<\/li>\n<li>Analyze, design and write verilog code for combinational logic circuits. (MUX, De-MUX, adder \u00a0and subtractor, and comparator circuits)<\/li>\n<li>Analyze and design code converters, encoders and decoders.<\/li>\n<li>Analyze and design of synchronous sequential circuits<\/li>\n<li>Analyze sequential circuits, Moore\/Mealy machines<\/li>\n<\/ul>\n<p><strong>Graduate Attributes (as per NBA)<\/strong><\/p>\n<ul>\n<li>Engineering knowledge<\/li>\n<li>Problem analysis<\/li>\n<li>Design &amp; Development of Solutions<\/li>\n<li>Modern tool usage<\/li>\n<\/ul>\n<p><strong>Question Paper Pattern<\/strong>:<\/p>\n<ul>\n<li>The question paper will have TEN questions.<\/li>\n<li>Each full question consists of 16 marks.<\/li>\n<li>There will be 2 full questions (with maximum of FOUR sub questions) from each module.<\/li>\n<li>Each full question will have sub questions covering all the topics under a module.<\/li>\n<li>The students will have to answer 5 full questions, selecting one full question from each module.<\/li>\n<\/ul>\n<p><strong>Text Books:<\/strong><\/p>\n<ul>\n<li>Digital Logic Applications and Design by John M Yarbrough, Thomson Learning,2001 (Modules\u00a01,2,3,4,5 \u2013Logic design)<\/li>\n<li>HDL Programming VHDL and Verilog by Nazeih M. Botros, 2009 reprint, Dreamtech\u00a0press.(Modules 1,2,3,4,5 Verilog description)<\/li>\n<\/ul>\n<p><strong>Reference Books:<\/strong><\/p>\n<ul>\n<li>Charles H Roth, Jr., \u201cFundamentals of logic design\u201d, Cengage Learning<\/li>\n<li>Digital Principals and Design \u2013 Donald D Givone,12th reprint, TMH,2008<\/li>\n<li>Logic Design, Sudhakar Samuel, Pearson\/ Saguine, 2007<\/li>\n<li>Fundamentals of HDL- Cyril P R Pearson\/Sanguin 2010<\/li>\n<\/ul>\n<p>For all other BE\/B.Tech 3rd Sem Subject syllabus do follow\u00a0<a href=\"https:\/\/www.inspirenignite.com\/vtu\/vtu-third-3rd-sem-biomedical-engineering\/\">VTU 3rd Sem BE \/ B.Tech Syllabus CBCS (2015-16) Scheme for Biomedical Engineering Group.<\/a><\/p>\n<p>For all other BE\/B.Tech 3rd Sem Subject syllabus do follow\u00a0<a href=\"https:\/\/www.inspirenignite.com\/vtu\/vtu-third-3rd-sem-electronics-instrumentation-engineering\/\">VTU 3rd Sem BE \/ B.Tech Syllabus CBCS (2015-16) Scheme for Electronics and Instrumentation Engineering Group.<\/a><\/p>\n<p>For all other BE\/B.Tech 3rd Sem Subject syllabus do follow\u00a0<a href=\"https:\/\/www.inspirenignite.com\/vtu\/vtu-third-3rd-sem-medical-electronics\/\">VTU 3rd Sem BE \/ B.Tech Syllabus CBCS (2015-16) Scheme for Medical Electronics Group.<\/a><\/p>\n<p>For more information about all VTU updates please stay connected to us on FB and don\u2019t hesitate to ask any questions in the comment.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Digital Design and HDL Syllabus for VTU BE\/B.Tech Biomedical Engineering third sem complete syllabus covered here. This will help you understand complete curriculum along with details such as exam marks [&hellip;]<\/p>\n","protected":false},"author":2259,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[4,32,13,15],"tags":[],"class_list":["post-561","post","type-post","status-publish","format-standard","hentry","category-3rd-sem","category-b-e-b-tech","category-bme","category-syllabus"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/561","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/users\/2259"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/comments?post=561"}],"version-history":[{"count":5,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/561\/revisions"}],"predecessor-version":[{"id":2960,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/561\/revisions\/2960"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/media?parent=561"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/categories?post=561"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/tags?post=561"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}