{"id":548,"date":"2016-09-09T11:35:35","date_gmt":"2016-09-09T11:35:35","guid":{"rendered":"http:\/\/www.inspirenignite.com\/vtu\/?p=548"},"modified":"2019-08-31T14:14:21","modified_gmt":"2019-08-31T14:14:21","slug":"digital-electronics-lab-syllabus-vtu-beb-tech","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/vtu\/digital-electronics-lab-syllabus-vtu-beb-tech\/","title":{"rendered":"Digital Electronics Lab Syllabus for VTU BE\/B.Tech CBCS 2015-16"},"content":{"rendered":"<p>Digital Electronics Lab Lab Syllabus for VTU BE\/B.Tech Nano Technology third sem complete syllabus covered here. This will help you understand complete curriculum along with details such as exam marks and duration. The details are as follows.<\/p>\n<table>\n<tbody>\n<tr>\n<th>Subject Code<\/th>\n<th>15NTL38<\/th>\n<th>IA Marks<\/th>\n<th>20<\/th>\n<\/tr>\n<tr>\n<td>Number of Lecture Hours\/Week<\/td>\n<td>01Hr Tutorial (Instructions) + 02 Hours Laboratory<\/td>\n<td>Exam Marks<\/td>\n<td>50<\/td>\n<\/tr>\n<tr>\n<td><\/td>\n<td><\/td>\n<td>Exam Hours<\/td>\n<td>3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>CREDITS \u2013 03<\/strong><\/p>\n<p><strong>Course objectives<\/strong>: This laboratory course enables students to:<\/p>\n<ul>\n<li>get practical experience in design, realisation and verification of Demorgan\u2019s Theorem, Full\/Parallel Adders and Subtractors, Multiplexer using logic gates, Demux and Decoder, Flip-Flops, Shift registers and Counters<\/li>\n<li>model, simulate and verify functionality of CMOS digital circuits<\/li>\n<\/ul>\n<table>\n<tbody>\n<tr>\n<th>Laboratory Experiments:NOTE: Use discrete components to test and verify the logic gates. Multisim may be used for designing the gates along with the above.<\/th>\n<th>Revised Bloom\u2019s Taxonomy (RBT) Level<\/th>\n<\/tr>\n<tr>\n<td>1. To verify (a) Demorgan\u2019s Theorem for 2 variables (b) The sum-of product and product-of-sum expressions using universal gates.<\/td>\n<td>L1, L2, L3<\/td>\n<\/tr>\n<tr>\n<td>\n<p style=\"text-align: center\"><a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\"><strong>Download iStudy App (No Ads, No PDFs) for complete VTU syllabus, results, timetables and all other updates.<\/strong><\/a><\/p>\n<\/td>\n<td>L5, L6<\/td>\n<\/tr>\n<tr>\n<td>3. To design and implement 4-bit Parallel Adder\/ subtractor using IC 7483.<\/td>\n<td>L5, L6<\/td>\n<\/tr>\n<tr>\n<td>4. To realize (a) 4:1 Multiplexer using gates (b) 3-variable function using IC 74151(8:1 MUX) (c) 1:8 Demux and 3:8 Decoder using IC74138<\/td>\n<td>L2, L3<\/td>\n<\/tr>\n<tr>\n<td>5. To realise the following flip-flops using NAND Gates. (a) Clocked SR Flip-Flop (b) JK Flip-Flop<\/td>\n<td>L2, L3<\/td>\n<\/tr>\n<tr>\n<td>6. To realize the following shift registers using IC7474 (a) SISO (b) SIPO (c)PISO (d) PIPO<\/td>\n<td>L2, L3<\/td>\n<\/tr>\n<tr>\n<td>7. To realize the Ring Counter and Johnson Counter using IC7476<\/td>\n<td>L2, L3<\/td>\n<\/tr>\n<tr>\n<td>8. To realize the Mod-N Counter using IC7490<\/td>\n<td>L2, L3<\/td>\n<\/tr>\n<tr>\n<td>9. To capture CMOS inverter schematic and check for its functionality (selecting suitable technology 130nm and below, connecting 0.01pF of load capacitance and setting lengths &amp; widths of transistor geometries)<\/td>\n<td>L4, L5, L6<\/td>\n<\/tr>\n<tr>\n<td>10. To capture schematic of NAND, NOR, AND using NAND and Inverter, OR using NOR &amp; Inverter. Verify functionality of gates using CMOS logic, measure propagation delay of gates by setting widths of transistors<\/td>\n<td>L4, L5, L6<\/td>\n<\/tr>\n<tr>\n<td>11. To capture schematic of 2:1 multiplexer using CMOS transmission gates and verify its functionality, extend the design for 4:1 multiplexer<\/td>\n<td>L4, L5, L6<\/td>\n<\/tr>\n<tr>\n<td>12. To capture schematic of XOR gate, XNOR gate, multiplexer based latch, master slave register and verify its functionality<\/td>\n<td>L4, L5, L6<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>Course outcomes<\/strong>: On the completion of this laboratory course, the students will be able to:<\/p>\n<ul>\n<li>Design, Test and Evaluate various combinational circuits such as adders, subtractors, multipliers,\u00a0comparators, parity generators, multiplexers and de-Multiplexers.<\/li>\n<li>Construct flips-flops, counters and shift registers and verify its functionality<\/li>\n<li>Model and verify CMOS digital circuits using MOS transistors<\/li>\n<\/ul>\n<p><strong>Graduate Attributes (as per NBA)<\/strong><\/p>\n<ul>\n<li>Engineering Knowledge.<\/li>\n<li>Problem Analysis.<\/li>\n<li>Design\/Development of solutions.<\/li>\n<\/ul>\n<p><strong>Conduct of Practical Examination:<\/strong><\/p>\n<ul>\n<li>All laboratory experiments are to be included for practical examination.<\/li>\n<li>Students are allowed to pick one experiment from the lot.<\/li>\n<li>Strictly follow the instructions as printed on the cover page of answer script for breakup of marks.<\/li>\n<li>Change of experiment is allowed only once and 15% Marks allotted to the procedure part to be\u00a0made zero.<\/li>\n<\/ul>\n<p><strong>Reference Book ( For 1 to 6 experiments):<\/strong><\/p>\n<ul>\n<li>K. A. Navas, \u201cElectronics Lab Manual\u201d, Volume I, PHI, 5th Edition, 2015, ISBN:9788120351424<\/li>\n<\/ul>\n<p><strong>Reference Book ( For 9 to 12 experiments):<\/strong><\/p>\n<ul>\n<li>Cyril Prasanna Raj P., \u201cCMOS digital circuit design manual\u201d, Volume 1, MSEC E-publication,\u00a0Edition 2016<\/li>\n<\/ul>\n<p>For all other BE\/B.Tech 3rd Sem Subject syllabus do follow\u00a0<a href=\"https:\/\/www.inspirenignite.com\/vtu\/vtu-third-3rd-sem-nano-technology\/\">VTU 3rd Sem BE \/ B.Tech Syllabus CBCS (2015-16) Scheme for Nano Technology Group.<\/a><\/p>\n<p>For more information about all VTU updates please stay connected to us on FB and don\u2019t hesitate to ask any questions in the comment.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Digital Electronics Lab Lab Syllabus for VTU BE\/B.Tech Nano Technology third sem complete syllabus covered here. This will help you understand complete curriculum along with details such as exam marks [&hellip;]<\/p>\n","protected":false},"author":2259,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[4,32,15],"tags":[],"class_list":["post-548","post","type-post","status-publish","format-standard","hentry","category-3rd-sem","category-b-e-b-tech","category-syllabus"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/548","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/users\/2259"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/comments?post=548"}],"version-history":[{"count":3,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/548\/revisions"}],"predecessor-version":[{"id":2933,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/548\/revisions\/2933"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/media?parent=548"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/categories?post=548"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/tags?post=548"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}