{"id":282,"date":"2016-09-01T08:40:47","date_gmt":"2016-09-01T08:40:47","guid":{"rendered":"http:\/\/www.inspirenignite.com\/vtu\/?p=282"},"modified":"2019-08-29T15:39:40","modified_gmt":"2019-08-29T15:39:40","slug":"vtu-b-e-b-tech-digital-electronics-laboratory","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/vtu\/vtu-b-e-b-tech-digital-electronics-laboratory\/","title":{"rendered":"Digital Electronics Laboratory Syllabus for VTU BE\/B.Tech CBCS 2015-16"},"content":{"rendered":"<p>Digital Electronics Laboratory Syllabus for VTU BE\/B.Tech Electronics and Communication \/Telecommunication Engineering third sem complete syllabus covered here. This will help you understand complete curriculum along with details such as exam marks and duration. The details are as follows.<\/p>\n<table>\n<tbody>\n<tr>\n<th>Laboratory Code<\/th>\n<th>15ECL38<\/th>\n<th>IA Marks<\/th>\n<th>20<\/th>\n<\/tr>\n<tr>\n<td>Number of Lecture Hours\/Week<\/td>\n<td>01Hr Tutorial (Instructions) + 02 Hours Laboratory<\/td>\n<td>Exam Marks<\/td>\n<td>50<\/td>\n<\/tr>\n<tr>\n<td><\/td>\n<td><\/td>\n<td>Exam Hours<\/td>\n<td>3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>CREDITS &#8211; 02<\/strong><\/p>\n<p><strong>Course Objectives:<\/strong><br \/>\nThis laboratory course enables students to get practical experience in design, realisation and verification of<\/p>\n<ul>\n<li>Demorgan\u2019s Theorem, SOP, POS forms<\/li>\n<li>Full\/Parallel Adders, Subtractors and Magnitude Comparator<\/li>\n<li>Multiplexer using logic gates<\/li>\n<li>Demultiplexers and Decoders<\/li>\n<li>Flip-Flops, Shift registers and Counters<\/li>\n<\/ul>\n<table>\n<tbody>\n<tr>\n<th>Laboratory Experiments:<br \/>\nNOTE: The experiments are to be carried using discrete components only.<\/th>\n<th>Revised Bloom\u2019s Taxonomy (RBT) Level<\/th>\n<\/tr>\n<tr>\n<td>1. Verify<br \/>\n(a) Demorgan\u2019s Theorem for 2 variables.<br \/>\n(b) The sum-of product and product-of-sum expressions using universal gates.<\/td>\n<td>L1, L2, L3, L4<\/td>\n<\/tr>\n<tr>\n<td style=\"text-align: center\"><strong><a href=\"https:\/\/play.google.com\/store\/apps\/details?id=ini.istudy\" target=\"_blank\" rel=\"noopener\">Download iStudy App (No Ads, No PDFs) for complete VTU syllabus, results, timetables and all other updates.<\/a><\/strong><\/td>\n<td>L3, L4<\/td>\n<\/tr>\n<tr>\n<td>3. Design and implement 4-bit Parallel Adder\/ subtractor using IC 7483.<\/td>\n<td>L3, L4, L5<\/td>\n<\/tr>\n<tr>\n<td>4. Design and Implementation of 4-bit Magnitude Comparator using IC 7485.<\/td>\n<td>L3, L4, L5<\/td>\n<\/tr>\n<tr>\n<td>5. Realize<br \/>\n(a) 4:1 Multiplexer using gates.<br \/>\n(b) 3-variable function using IC 74151(8:1MUX).<\/td>\n<td>L2, L3, L4<\/td>\n<\/tr>\n<tr>\n<td>6. Realize 1:8 Demux and 3:8 Decoder using IC74138.<\/td>\n<td>L2, L3, L4<\/td>\n<\/tr>\n<tr>\n<td>7. Realize the following flip-flops using NAND Gates.<br \/>\n(a) Clocked SR Flip-Flop<br \/>\n(b) JK Flip-Flop.<\/td>\n<td>L2, L3<\/td>\n<\/tr>\n<tr>\n<td>8. Realize the following shift registers using IC7474<br \/>\n(a) SISO (b) SIPO (c) PISO (d)PIPO.<\/td>\n<td>L2, L3<\/td>\n<\/tr>\n<tr>\n<td>9. Realize the Ring Counter and Johnson Counter using IC7476.<\/td>\n<td>L2, L3<\/td>\n<\/tr>\n<tr>\n<td>10. Realize the Mod-N Counter using IC7490.<\/td>\n<td>L2, L3<\/td>\n<\/tr>\n<tr>\n<td>11. Simulate Full- Adder using simulation tool<\/td>\n<td>L2, L3, L4<\/td>\n<\/tr>\n<tr>\n<td>12. Simulate Mod-8 Synchronous UP\/DOWN Counter using simulation tool.<\/td>\n<td>L2, L3, L4<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>Course outcomes:<\/strong> On the completion of this laboratory course, the students will be able to:<\/p>\n<ul>\n<li>Demonstrate the truth table of various expressions and combinational circuits using logic gates.<\/li>\n<li>Design, test and evaluate various combinational circuits such as adders, subtractors, comparators, multiplexers and demultiplexers.<\/li>\n<li>Construct flips-flops, counters and shift registers.<\/li>\n<li>Simulate full adder and up\/down counters.<\/li>\n<\/ul>\n<p><strong>Graduate Attributes (as per NBA) <\/strong><\/p>\n<ul>\n<li>Engineering Knowledge.<\/li>\n<li>Problem Analysis.<\/li>\n<li>Design\/Development of solutions.<\/li>\n<\/ul>\n<p><strong>Conduct of Practical Examination: <\/strong><\/p>\n<ul>\n<li>All laboratory experiments are to be included for practical examination.<\/li>\n<li>Students are allowed to pick one experiment from the lot.<\/li>\n<li>Strictly follow the instructions as printed on the cover page of answer script for breakup of marks.<\/li>\n<li>Change of experiment is allowed only once and 15% Marks allotted to the procedure part to be made zero.<\/li>\n<\/ul>\n<p><strong>NOTE<\/strong>: For experiment 11 and 12 any open source or licensed simulation tool may be used.<\/p>\n<p>For all other BE\/B.Tech 3rd Sem Subject syllabus do follow&nbsp;<a href=\"https:\/\/www.inspirenignite.com\/vtu\/vtu-third-3rd-sem-electronics-communication-engineering-telecommunication-engineering\/\">VTU 3rd Sem BE \/ B.Tech Syllabus CBCS (2015-16) Scheme for Electronics &amp; Communication and Telecommunication Engineering Group.<\/a><\/p>\n<p>For more information about all VTU updates please stay connected to us on FB and don\u2019t hesitate to ask any questions in the comment.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Digital Electronics Laboratory Syllabus for VTU BE\/B.Tech Electronics and Communication \/Telecommunication Engineering third sem complete syllabus covered here. This will help you understand complete curriculum along with details such as [&hellip;]<\/p>\n","protected":false},"author":2259,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[4,32,15],"tags":[],"class_list":["post-282","post","type-post","status-publish","format-standard","hentry","category-3rd-sem","category-b-e-b-tech","category-syllabus"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/282","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/users\/2259"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/comments?post=282"}],"version-history":[{"count":5,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/282\/revisions"}],"predecessor-version":[{"id":2784,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/282\/revisions\/2784"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/media?parent=282"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/categories?post=282"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/tags?post=282"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}