{"id":10546,"date":"2020-02-21T16:26:37","date_gmt":"2020-02-21T16:26:37","guid":{"rendered":"https:\/\/www.inspirenignite.com\/vtu\/15ec65p-verilog-lab-electronics-6th-sem-syllabus-for-diploma-dte-karnataka-c15-scheme\/"},"modified":"2020-02-21T16:26:37","modified_gmt":"2020-02-21T16:26:37","slug":"15ec65p-verilog-lab-electronics-6th-sem-syllabus-for-diploma-dte-karnataka-c15-scheme","status":"publish","type":"post","link":"https:\/\/www.inspirenignite.com\/vtu\/15ec65p-verilog-lab-electronics-6th-sem-syllabus-for-diploma-dte-karnataka-c15-scheme\/","title":{"rendered":"15EC65P: Verilog Lab Electronics 6th Sem Syllabus for Diploma DTE Karnataka C15 Scheme"},"content":{"rendered":"

Verilog Lab detail DTE Kar Diploma syllabus for Electronics And Communication Engineering (EC), C15 scheme is extracted from DTE Karnataka<\/a> official website and presented for diploma students. The course code (15EC65P), and for exam duration, Teaching Hr\/week, Practical Hr\/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below. The syllabus PDFs can be downloaded from official website.<\/p>\n

For all other electronics 6th sem syllabus for diploma c15 scheme dte karnataka you can visit Electronics 6th Sem Syllabus for Diploma C15 Scheme DTE Karnataka Subjects<\/a>. The detail syllabus for verilog lab is as follows.<\/p>\n

Pre-requisites:<\/h4>\n

Knowledge of basic Mathematics, digital electronic circuits and Programming languages.\n<\/p>\n

Course Objectives:<\/h4>\n

Learn and understand the basics of Hardware description language and its use in designing electronic circuits.\n<\/p>\n

Course Outcomes:<\/h4>\n

For complete syllabus and results, class timetable and more pls download iStudy Syllabus App<\/a>.<\/b> Its a light weight, easy to use, no images, no pdfs platform to make students life easier.<\/p>\n

UNIT – 1: Tutorial and Practice Duration: 24 Hrs
\n<\/h4>\n
    \n
  1. Evolution of Computer-Aided digital design, Introduction to HDL, Importance of HDL, levels of abstraction, typesof code-Structural and procedural.\t3<\/li>\n
  2. Introduction to Verilog HDL, Definition, Program Structure of Verilog, Lexical Tokens\/Conventions-explain with syntax-White Space, Comments, Numbers, Identifiers, Operators, Verilog Keywords. Data types-explain with syntax-Value Set, Wire, Reg, Input, Output, Inout Integer, Supply0, Supply1, Time, Parameter. Simple examples.\t3<\/li>\n
  3. Operators with examples-Arithmetic, Logical, Relational, Bit-wise, Reduction, Shift, concatenation, Replication, Conditional operators. Operator Precedence.\t3<\/li>\n
  4. Operands-explain with syntax-Literals, Wires, Regs, and Parameters, BitSelects, Part-Selects, Function Calls. Simple examples.\t3<\/li>\n
  5. Modules-Module Declaration, Continuous Assignment, Module Instantiations, Parameterized Modules, Procedures: Always and Initial Blocks. Simple examples.\t3<\/li>\n
  6. Tasks and Functions-display, strobe, monitor, reset, stop, finish etc. Timing Control-Delay Control(#), Events, wait Statement, join Statements.\t3<\/li>\n
  7. Behavioral Modeling-Procedural Assignments, Delay in Assignment, Blocking Assignments, Non-blocking (RTL) Assignments, begin .. end, for Loops, while Loops, forever Loops, if .. else if .. else, disable, case. Simple examples.\t3<\/li>\n
  8. Functions-Function Declaration, Return Value, Call, Function Rules, Simple Examples. Brief description about Gate-Level Modeling,Dataflow Modeling, Switch-Level Modeling.\t3<\/li>\n<\/ol>\n

    Practice Exercises<\/b><\/p>\n

    Write and execute verilog code for the following problems<\/p>\n

      \n
    1. Verilog Description for all two input basic gates.<\/li>\n
    2. Verilog Description for two input Arithmetic operations.<\/li>\n
    3. Verilog Description for three\/four input Logical operations.<\/li>\n
    4. Compute the output for arithmetic expression. y=(a+b*c)\/(a+c)<\/li>\n
    5. Compute the output for Logical expression. y= (A and B) or (B and C).<\/li>\n
    6. Verilog Description for 1-bit Full Adder<\/li>\n
    7. Verilog Description for 2:1 multiplexer using dataflow\/behavioral method.<\/li>\n
    8. Verilog Description for 1:2 De-multiplexer using dataflow\/behavioral method.<\/li>\n
    9. Verilog Description for 2-bit parallel adder.<\/li>\n
    10. Verilog Description for 2-bit ALU with any 2 arithmetic and logical operations.<\/li>\n
    11. Verilog Code for D-flipflop<\/li>\n
    12. Verilog Code for T-flipflop<\/li>\n
    13. Verilog Description for mod-6 counter.<\/li>\n<\/ol>\n

      UNIT – 2: Graded Exercises Duration: 48 Hr
      \n<\/h4>\n

      Write the verilog code for the following problems and simulate using any HDL simulator\/synthesis software (Xilinx\/Modelsim\/Simulink etc) and download to FPGA\/CPLD trainerkits.<\/p>\n

        \n
      1. <\/li>\n
          \n
        1. Verilog description for full-adder using structural modeling.<\/li>\n
        2. Verilog description for full-adder using behavioral modeling.\t3<\/li>\n<\/ol>\n
        3. Verilog description for 4-bit ripple carry full-adder using 1-bit full-adder.\t3<\/li>\n
        4. <\/li>\n
            \n
          1. Verilog description for BCD to seven segment decoder for common anode display using if else.<\/li>\n
          2. Verilog description for BCD to seven segment decoder using case statement.\t3<\/li>\n<\/ol>\n
          3. <\/li>\n
              \n
            1. Verilog description for 4 -bit parallel adder.<\/li>\n
            2. Verilog description for 4-bit comparator.\t3<\/li>\n<\/ol>\n
            3. <\/li>\n
                \n
              1. Verilog description for 4-bit ALU with threelogical & three arithmetic operations.<\/li>\n
              2. Verilog description for any threerelational and three bit-wise operations.\t3<\/li>\n<\/ol>\n
              3. <\/li>\n
                  \n
                1. Verilog description for 4-to-1 multiplexer using logic equations.<\/li>\n
                2. Verilog description for 4-to-1 multiplexer using conditional operators.<\/li>\n
                3. Verilog description for 4-to-1 multiplexer using behavioral modeling.<\/li>\n
                4. Verilog description for 4-to-1 multiplexer using 2:1 muxes.\t6<\/li>\n<\/ol>\n
                5. <\/li>\n
                    \n
                  1. Verilog description for clocked T-flip flop.<\/li>\n
                  2. Verilog description for edge-triggered D-flip flop.\t3<\/li>\n<\/ol>\n
                  3. <\/li>\n
                      \n
                    1. Verilog description for edge-triggered JK-flip flop.<\/li>\n
                    2. Verilog description for 4-bit counter using JK-flip flop.\t6<\/li>\n<\/ol>\n
                    3. <\/li>\n
                        \n
                      1. Verilog description for BCD up\/down counter using behavior modeling.<\/li>\n
                      2. Verilog description for 4-bit ripple carry counter using T and D-flip flop.\t3<\/li>\n<\/ol>\n
                      3. Verilog description for universal shift register.\t3<\/li>\n
                      4. Two open-ended experiments of similar nature as above are to be assigned by the teacher. Student is expected to solve and execute\/simulate independently using verilog code.\t6<\/li>\n<\/ol>\n

                        Unit – 3: Student Activities [CIE- 05 Marks] 06 Hours & off-classes<\/p>\n

                        For complete syllabus and results, class timetable and more pls download iStudy Syllabus App<\/a>.<\/b> Its a light weight, easy to use, no images, no pdfs platform to make students life easier.<\/p>\n

                        Reference Books:<\/h4>\n
                          \n
                        1. Fundamentals of Digital logic with Verilog design-2e, Brown Vranesic, McGrawHill education, ISBN-13:978-0-07-066724-2.<\/li>\n
                        2. Verilog HDL-A guide to Digital Design and Synthesis-Samir Palnitkar-ISBN: 0134516753; Pub: Prentice Hall PTR.<\/li>\n
                        3. Introduction to Verilog-.Peter M. Nyasulu.<\/li>\n
                        4. Handbook on Verilog HDL-Dr. Daniel C. Hyde,Bucknell University<\/li>\n
                        5. Verilog Tutorial – Deepak Kumar Tala<\/li>\n
                        6. The Verilog Hardware Description Language-Donald Thomas and Philip Moorby (2008)<\/li>\n
                        7. http:\/\/www.iitk.ac.in\/eclub\/summercamp\/Courses\/CompArch\/Verilog lab Solutions.pdf<\/li>\n
                        8. http:\/\/users.ece.utexas.edu\/~ljohn\/teaching\/ee460m lab manual.pdf<\/li>\n
                        9. http:\/\/treymorris.com\/classes\/elen\/248\/lab\/lab%20manuals\/lab manual 5.pdf<\/li>\n
                        10. http:\/\/d1.amobbs.com\/bbs upload782111\/files 33\/ourdev 585395BQ8J9A.pdf<\/li>\n
                        11. www.cc.gatech.edu\/~hadi\/..\/01..\/verilog\/An%20Introduction%20to%20Verilog.pdf<\/li>\n
                        12. www.ece.niu.edu.tw\/~chu\/download\/fpga\/verilog.pdf<\/li>\n
                        13. http:\/\/www.asic-world.com\/<\/li>\n
                        14. https:\/\/www.youtube.com\/watch?v=QSEl O0Gtoo&list=PLoM0uG7tqR3qVss3zhBRniXU7mhHy2bwj<\/li>\n<\/ol>\n

                          Course Delivery:<\/h4>\n

                          The course will be normally delivered through two-hour tutorials and four-hour hands-on practice per week; hands-on practice shall include verilog simulation programs. Normally, one-hour tutorial followed by two-hour hands-on practice is recommended in each class. Tutorial shall be imparted before the conduction of the experiment. However, activities are carried-out off-class and demonstration\/presentation can be in lab sessions.\n<\/p>\n

                          Student Activity (5 marks):<\/h4>\n

                          For complete syllabus and results, class timetable and more pls download iStudy Syllabus App<\/a>.<\/b> Its a light weight, easy to use, no images, no pdfs platform to make students life easier.<\/p>\n

                          Execution Notes:<\/h4>\n
                            \n
                          1. Each batch of 2 students is assigned at least one activity listed in Unit-3 based on interest of the students. Student can also choose any other similar \/relevant activity with prior approval from the concerned teacher.<\/li>\n
                          2. Teacher is expected to observe and record the progress of students activities<\/li>\n
                          3. Assessment is made based on quality of work as prescribed by the table<\/li>\n<\/ol>\n

                            Model Questions for Practice and Semester End Examination<\/h4>\n<\/p>\n

                            Note: The questions in the question bank are indicative but not exhaustive.<\/i><\/p>\n

                              \n
                            1. Write a verilog code for half-adder and full-adder using behavioral modelling.<\/li>\n
                            2. Write a verilog code for half-subtractor and full-subtractor using behavioural modeling.<\/li>\n
                            3. Write a verilog code for 4-bit full-adder, Using Dataflow Operators.<\/li>\n
                            4. Write a verilog code for 4 bit parallel adder.<\/li>\n
                            5. Write a verilog code for BCD to seven segment decoder.<\/li>\n
                            6. Write a verilog code for 4 bit parallel adder.<\/li>\n
                            7. Write a verilog codefor 4 bit comparator.<\/li>\n
                            8. Write a verilog codefor 4-to-1 multiplexer, using logic equations.<\/li>\n
                            9. Write a verilog codefor 4-to-1 multiplexer, using conditional operators.<\/li>\n
                            10. Write a verilog codefor behavioral 4-to-1 multiplexer.<\/li>\n
                            11. Write a verilog codefor1:4 de-multiplexer, using logic equations.<\/li>\n
                            12. Write a verilog codefor1:4 de-multiplexer using behavioralmodeling.<\/li>\n
                            13. Write a verilog code for clocked T-flipflop.<\/li>\n
                            14. Write a verilog code for edge-triggered D-flipflop.<\/li>\n
                            15. Write a verilog code for edge-triggered JK-flipflop<\/li>\n
                            16. Write a verilog code forripple counter<\/li>\n
                            17. Write a verilog code forbehavioral 4-bit counter.<\/li>\n
                            18. Write a verilog code foruniversal shift register\/left-right shifter using function.<\/li>\n
                            19. Write a Switch-level verilogdescription of 2-to-1 multiplexer.<\/li>\n
                            20. Write a Switch-level verilogdescription of CMOS inverter.<\/li>\n
                            21. Write a Switch-level verilog for NOR-gate<\/li>\n
                            22. Write a verilog code for 4-bit ALU with 3 logical & 3 arithmetic operations<\/li>\n
                            23. Write a verilog code for any 2 relational and 2-bit-wise operations<\/li>\n<\/ol>\n

                              For detail syllabus of all other subjects of BE Electronics, C15 scheme do visit Electronics 6th Sem syllabus for C15 scheme<\/a>.<\/p>\n

                              Dont forget to download iStudy Syllabus App<\/a> for latest syllabus and results, class timetable and more.<\/p>\n","protected":false},"excerpt":{"rendered":"

                              Verilog Lab detail DTE Kar Diploma syllabus for Electronics And Communication Engineering (EC), C15 scheme is extracted from DTE Karnataka official website and presented for diploma students. The course code […]<\/p>\n","protected":false},"author":2298,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_bbp_topic_count":0,"_bbp_reply_count":0,"_bbp_total_topic_count":0,"_bbp_total_reply_count":0,"_bbp_voice_count":0,"_bbp_anonymous_reply_count":0,"_bbp_topic_count_hidden":0,"_bbp_reply_count_hidden":0,"_bbp_forum_subforum_count":0,"footnotes":""},"categories":[19,64],"tags":[],"class_list":["post-10546","post","type-post","status-publish","format-standard","hentry","category-6th-sem","category-ec-diploma"],"_links":{"self":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/10546","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/users\/2298"}],"replies":[{"embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/comments?post=10546"}],"version-history":[{"count":0,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/posts\/10546\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/media?parent=10546"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/categories?post=10546"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.inspirenignite.com\/vtu\/wp-json\/wp\/v2\/tags?post=10546"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}