Digital Electronics Syllabus VTU BE/B.Tech Electronics and Communication /Telecommunication Engineering III sem is covered here. This will help you get a complete picture of the modules in this subject including subtopics in each module. Further, information about exam marks, duration of the course and the credits is provided. The details are as follows.
| Subject Code | 15EC33 | IA Marks | 20 |
|---|---|---|---|
| Number of Lecture Hours/Week | 4 | Exam Marks | 80 |
| Total Number of Lecture Hours | 50 | Exam Hours | 3 |
CREDITS – 04
Digital Electronics Syllabus VTU CBCS 2015-16
Course Objectives:
This course will enable students to:
- Describe, Illustrate and Analyze Combinational Logic circuits, Simplification of Algebraic Equations using Karnaugh Maps and Quine McClusky Techniques.
- Define and Describe Decoders, Encoders, Digital multiplexers, Adders and Subtractors, Binary comparators, Latches and Master-Slave Flip-Flops.
- Describe, Demonstrate, Analyze and Design of Mealy and Moore Models, Synchronous Sequential Circuits, State diagrams and Registers and Counters.
| Modules | Teaching Hour | Revised Bloom’s Taxonomy (RBT) Level |
|---|---|---|
| Module -1 | _ | |
| Principles of combination logic: Definition of combinational logic, canonical forms, Generation of switching equations from truth tables, Karnaugh maps-3,4,5 variables, Incompletely specified functions( Don’t care terms) Simplifying Max term equations, Quine-McCluskey minimization technique, QuineMcCluskey using don’t care terms, Reduced prime implicants Tables. (Text 1, Chapter 3) | 10 Hours | L1, L2,L3 |
| Module -2 | _ | |
| Download iStudy App (No Ads, No PDFs) for complete VTU syllabus, results, timetables and all other updates. | 10 Hours | L1, L2,L3 |
| Module -3 | _ | |
| Flip-Flops: Basic Bistable elements, Latches, Timing considerations, The master-slave flip-flops( pulse-triggered flip-flops): SR flip-flops, JK flip-flops, Edge triggered flip-flops, Characteristic equations. (Text 2, Chapter 6) | 10 Hours | L1, L2 |
| Module -4 | _ | |
| Simple Flip-Flops Applications: Registers, binary ripple counters, synchronous binary counters, Counters based on shift registers, Design of a synchronous counters, Design of a synchronous mod-n counter using clocked T , JK , D and SR flip-flops. (Text 2, Chapter 6) | 10 Hours | L1, L2 |
| Module -5 | _ | |
| Sequential Circuit Design: Mealy and Moore models, State machine notation , Synchronous Sequential circuit analysis, Construction of state diagrams, counter design. (Text 1, Chapter 6) | 10 Hours | L2, L3,L4 |
Course outcomes:
After studying this course, students will be able to:
- Acquire knowledge of o Combinational Logic. o Simplification Techniques using Karnaugh Maps, Quine-McClusky Technique. Operation of Decoders, Encoders, Multiplexers, Adders and Subtractors.
- Working of Latches, Flip-Flops, o Designing Registers, Counters.
- Mealy, Moore Models and State Diagrams
- Analyse the performance of
Simplification Techniques using Karnaugh Maps, Quine-McClusky Technique.
Synchronous Sequential Circuits. - Design and Develop Mealy and Moore Models for digital circuits.
Apply the knowledge gained in the design of Counters and Registers.
Graduate Attributes (as per NBA):
- Engineering Knowledge.
- Problem Analysis.
- Design / development of solutions (partly).
- Interpretation of data.
Question paper pattern:
- The question paper will have ten questions.
- Each full question consists of 16 marks.
- There will be 2 full questions (with a maximum of four sub questions) from each module.
Each full question will have sub questions covering all the topics under a module. The students will have to answer 5 full questions, selecting one full question from each module.
Text Books:
- Digital Logic Applications and Design, John M Yarbrough, Thomson Learning, 2001. ISBN 981-240-062-1.
- Donald D. Givone, “Digital Principles and Design”, Mc Graw Hill, 2002. ISBN 978-0-07-052906-9.
Reference Books:
- D. P. Kothari and J. S Dhillon, “Digital Circuits and Design”, Pearson, 2016, ISBN:9789332543539.
- Morris Mano, ―Digital design, Prentice Hall of India, Third Edition.
- Charles H Roth, Jr., “Fundamentals of logic design”, Cengage Learning.
- K. A. Navas, “Electronics Lab Manual”, Volume I, PHI, 5th Edition, 2015, ISBN:9788120351424.
For all other BE/B.Tech 3rd Sem Subject syllabus do follow VTU 3rd Sem BE / B.Tech Syllabus CBCS (2015-16) Scheme for Electronics & Communication and Telecommunication Engineering Group.
For more information about all VTU updates please stay connected to us on FB and don’t hesitate to ask any questions in the comment.