Vlsi Lab detail syllabus for Electronics & Communication Engineering (Ece), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17ECL77), and for exam duration, Teaching Hr/week, Practical Hr/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.
For all other ece 7th sem syllabus for be 2017 scheme vtu you can visit ECE 7th Sem syllabus for BE 2017 Scheme VTU Subjects. The detail syllabus for vlsi lab is as follows.
Course Objectives:
This course will enable students to:
- Explore the CAD tool and understand the flow of the Full Custom IC design cycle.
- Learn DRC, LVS and Parasitic Extraction of the various designs.
- Design and simulate the various basic CMOS analog circuits and use them in higher circuits like data converters using design abstraction concepts.
- Design and simulate the various basic CMOS digital circuits and use them in higher circuits like adders and shift registers using design abstraction concepts.
Experiments can be conducted using any of the following or equivalent design tools: Cadence/Synopsis/Mentor Graphics/Microwind
Laboratory Experiments:
For complete syllabus and results, class timetable and more pls download iStudy. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.
Part – A:
ASIC-DIGITAL DESIGN
- Write Verilog Code for the following circuits and their Test Bench for verification, o[SAR]
Part – B:
ANALOG DESIGN
- Design an Inverter with given specifications**, completing the design flow mentioned below:
- Draw the schematic and verify the following
- DC Analysis
- Transient Analysis
- Draw the Layout and verify the DRC, ERC
- Check for LVS
- Extract RC and back annotate the same and verify the Design
- Verify & Optimize for Time, Power and Area to the given constraint*
- Design the
- Common source and Common Drain amplifier and
- A Single Stage differential amplifier, with given specifications**, completing the
- Draw the schematic and verify the following
- DC Analysis
- AC Analysis
- Transient Analysis
- Draw the Layout and verify the DRC, ERC
- Check for LVS
- Extract RC and back annotate the same and verify the Design.
- Design an op-amp with given specification** using given differential amplifier Common source and Common Drain amplifier in library*** and completing the design flow mentioned below:
- Draw the schematic and verify the following
- DC Analysis
- . AC Analysis
- Transient Analysis
- Draw the Layout and verify the DRC, ERC
- Check for LVS
- Extract RC and back annotate the same and verify the Design.
- Design a 4 bit R-2R based DAC for the given specification and completing the
- Draw the schematic and verify the following
- DC Analysis
- AC Analysis
- Transient Analysis
- Draw the Layout and verify the DRC, ERC
- For the SAR based ADC mentioned in the figure below draw the mixed signal schematic and verify the functionality by completing ASIC Design FLOW.
design flow mentioned below:
design flow mentioned using given op-amp in the library***.
*
An appropriate constraint should be given.
** Appropriate specification should be given.
*** Applicable Library should be added & information should be given to the Designer.
Course Outcomes:
For complete syllabus and results, class timetable and more pls download iStudy. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.
Conduct of Practical Examinations:
- All practicals are to be included for practical examination.
- For examination, one question from PART.A and one question from PART.B to be set.
- Students are allowed to pick one experiment from the lot.
- Change of experiment is allowed only once and Marks allotted to the procedure part to be made zero.
For detail syllabus of all other subjects of BE Ece, 2017 scheme do visit Ece 7th Sem syllabus for 2017 scheme.
Dont forget to download iStudy for latest syllabus and results, class timetable and more.