Vlsi Design Med Elec 5th Sem Syllabus for VTU BE 2017 Scheme (Professional Elective-I)

Vlsi Design detail syllabus for Medical Electronics (Med Elec), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17ML551), and for exam duration, Teaching Hr/week, Practical Hr/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.

For all other med elec 5th sem syllabus for be 2017 scheme vtu you can visit Med Elec 5th Sem syllabus for BE 2017 Scheme VTU Subjects. For all other Professional Elective-I subjects do refer to Professional Elective-I. The detail syllabus for vlsi design is as follows.

Module 1

Moores law, speed power performance, nMOS fabrication, CMOS fabrication: n-well, p-well processes, BiCMOS, Comparison of bipolar and CMOS. Basic Electrical Properties of MOS And BiCMOS Circuits: Drain to source current versus voltage characteristics, threshold voltage, transconductance.

Module 2

For complete syllabus and results, class timetable and more pls download iStudy. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.

Module 3

MOS and BiCMOS Circuit Design Processes: MOS layers, stick diagrams, nMOS design style, CMOS design style, design rules and layout, X – based design. Scaling of MOS Circuits: scaling factors for device parameters, limitations of scaling.

Module 4

Subsystem Design and Layout-1 : Switch logic pass transistor, Gate logic inverter, NAND gates, NOR gates, pseudo nMOS, Dynamic CMOS, example of structured design, Parity generator, Bus arbitration, multiplexers, logic function block, code converter. Subsystem Design and Layout-2 : Clocked sequential circuits, dynamic shift registers, bus lines, subsystem design processes, General considerations, 4-bit arithmetic processes, 4-bit shifter.

Module 5

For complete syllabus and results, class timetable and more pls download iStudy. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.

Course Outcomes:

After studying this course, students will able to;

1. Identify the CMOS layout levels, and the design layers used in the process sequence.
2. Describe the general steps required for processing of CMOS integrated circuits.
3. Design static CMOS combinational and sequential logic at the transistor level.
4. Demonstrate different logic styles such as complementary CMOS logic, pass-transistor Logic, dynamic logic, etc.
5. Interpret the need for testability and testing methods in VLSI.

Question paper pattern:

• The question paper will have TEN questions.
• Each full question carry16marks
• There will be TWO full questions (with maximum of THREE sub questions) from each module.
• Each full question will have sub questions covering all the topics under a module.
• The students will have to answer FIVE full questions, selecting ONE full question from each module.

Text Books:

1. Basic VLSI Design -3rd Edition Douglas A Pucknell, Kamaran Eshraghian, Prentice Hall of India publication, 2005.

Reference Books:

1. CMOS Digital Integrated Circuits, Analysis And Design, 3rd Edition, Sung – Mo (Steve) Kang, Yusuf Leblbici, Tata McGraw Hill, 2002.
2. VLSI Technology – S.M. Sze, 2nd edition Tata McGraw Hill, 2003.

For detail syllabus of all other subjects of BE Med Elec, 2017 regulation do visit Med Elec 5th Sem syllabus for 2017 Regulation.

Dont forget to download iStudy for latest syllabus and results, class timetable and more.