Vlsi Design detail syllabus for Electronics & Communication Engineering (Ece), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17EC63), and for exam duration, Teaching Hr/week, Practical Hr/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.
For all other ece 6th sem syllabus for be 2017 scheme vtu you can visit ECE 6th Sem syllabus for BE 2017 Scheme VTU Subjects. The detail syllabus for vlsi design is as follows.
Course Objectives:
The objectives of the course is to enable students to:
- Impart knowledge of MOS transistor theory and CMOS technologies
- Impart knowledge on architectural choices and performance tradeoffs involved in designing and realizing the circuits in CMOS technology
- Cultivate the concepts of subsystem design processes
- Demonstrate the concepts of CMOS testing
Module 1
For complete syllabus and results, class timetable and more pls download iStudy. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.
Module 2
MOS and BiCMOS Circuit Design Processes: MOS Layers, Stick Diagrams, Design Rules and Layout. Basic Circuit Concepts: Sheet Resistance, Area Capacitances of Layers, Standard Unit of Capacitance, Some Area Capacitance Calculations, Delay Unit, Inverter Delays, Driving Large Capacitive Loads (3.1 to 3.3, 4.1, 4.3 to 4.8 of TEXT1).
Module 3
Scaling of MOS Circuits: Scaling Models & Scaling Factors for Device Parameters Subsystem Design Processes: Some General considerations, An illustration of Design Processes, Illustration of the Design Processes- Regularity, Design of an ALU Subsystem, The Manchester Carry-chain and Adder Enhancement Techniques(5.1, 5.2, 7.1, 7.2, 8.2, 8.3, 8.4.1, 8.4.2 of TEXT1).
Module 4
For complete syllabus and results, class timetable and more pls download iStudy. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.
Module 5
Memory, Registers and Aspects of system Timing- System Timing Considerations, Some commonly used Storage/Memory elements (9.1, 9.2 of TEXT1). Testing and Verification: Introduction, Logic Verification, Logic Verification Principles, Manufacturing Test Principles, Design for testability (12.1, 12.1.1, 12.3, 12.5, 12.6 of TEXT 2).
Course Outcomes:
At the end of the course, the students will be able to:
- Demonstrate understanding of MOS transistor theory, CMOS fabrication flow and technology scaling.
- Draw the basic gates using the stick and layout diagrams with the knowledge of physical design aspects.
- Interpret Memory elements along with timing considerations
- Demonstrate knowledge of FPGA based system design
- Interpret testing and testability issues in VLSI Design
- Analyze CMOS subsystems and architectural issues with the design constraints.
Text Books:
- Basic VLSI Design- Douglas A. Pucknell& Kamran Eshraghian, PHI 3rd Edition (original Edition – 1994).
- CMOS VLSI Design- A Circuits and Systems Perspective- Neil H.E. Weste, David Harris, Ayan Banerjee, 3rd Edition, Pearson Education.
- FPGA Based System Design- Wayne Wolf, Pearson Education, 2004, Technology and Engineering.
For detail syllabus of all other subjects of BE Ece, 2017 scheme do visit Ece 6th Sem syllabus for 2017 scheme.
Dont forget to download iStudy for latest syllabus and results, class timetable and more.