Verilog Hdl ECE 5th Sem Syllabus for VTU BE 2017 Scheme

Verilog Hdl detail syllabus for Electronics & Communication Engineering (Ece), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17EC53), and for exam duration, Teaching Hr/week, Practical Hr/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.

For all other ece 5th sem syllabus for be 2017 scheme vtu you can visit ECE 5th Sem syllabus for BE 2017 Scheme VTU Subjects. The detail syllabus for verilog hdl is as follows.

Course Objectives:

This course will enable students to:

• Differentiate between Verilog and VHDL descriptions.
• Learn different Verilog HDL and VHDL constructs.
• Familiarize the different levels of abstraction in Verilog.
• Understand Verilog Tasks and Directives.
• Understand timing and delay Simulation.
• Learn VHDL at design levels of data flow, behavioral and structural for effective modeling of digital circuits.

Module 1

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Module 2

Basic Concepts Lexical conventions, data types, system tasks, compiler directives. (Text1) Modules and Ports Module definition, port declaration, connecting ports, hierarchical name referencing. (Text1)

Module 3

Gate-Level Modeling Modeling using basic Verilog gate primitives, description of and/or and buf/not type gates, rise, fall and turn-off delays, min, max, and typical delays. (Text1) Dataflow Modeling Continuous assignments, delay specification, expressions, operators, operands, operator types. (Text1)

Module 4

For complete syllabus and results, class timetable and more pls download iStudy. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.

Module 5

Introduction to VHDL Introduction: Why use VHDL?, Shortcomings, Using VHDL for Design Synthesis,
Design tool flow, Font conventions.
Entities and Architectures: Introduction, A simple design, Design entities, Identifiers, Data objects, Data types, and Attributes. (Text 2)

Course Outcomes:

At the end of this course, students should be able to

• Write Verilog programs in gate, dataflow (RTL), behavioral and switch modeling levels of Abstraction.
• Write simple programs in VHDL in different styles.
• Design and verify the functionality of digital circuit/system using test benches.
• Identify the suitable Abstraction level for a particular digital design.
• Write the programs more effectively using Verilog tasks and directives.
• Perform timing and delay Simulation.

Text Books:

1. Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Pearson Education, Second Edition.
2. Kevin Skahill, VHDL for Programmable Logic, PHI/Pearson education, 2006.

Reference Books:

1. Donald E. Thomas, Philip R. Moorby, The Verilog Hardware Description Language, Springer Science+Business Media, LLC, Fifth edition.
2. Michael D. Ciletti, Advanced Digital Design with the Verilog HDL Pearson (Prentice Hall), Second edition.
3. Padmanabhan, Tripura Sundari, Design through Verilog HDL, Wiley, 2016 or earlier.

For detail syllabus of all other subjects of BE Ece, 2017 scheme do visit Ece 5th Sem syllabus for 2017 scheme.

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