Mosfets and Digital Circuits detail syllabus for Nanoelectronics (Nano), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17NT34), and for exam duration, Teaching Hr/week, Practical Hr/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.
For all other nano 3rd sem syllabus for be 2017 scheme vtu you can visit Nano 3rd Sem syllabus for BE 2017 Scheme VTU Subjects. The detail syllabus for mosfets and digital circuits is as follows.
Course Objectives:
This course will enable students to:
- Describe, Illustrate and Analyze MOS transistor theory, MOS VI characteristics, NMOS and PMOS transistor and CMOS technology
- Define and describe realization of digital circuits using CMOS technology
- Describe, Demonstrate, Analyze and Design of Mealy and Moore Models, Synchronous Sequential Circuits, State diagrams and Registers and Counters.
Module 1
For complete syllabus and results, class timetable and more pls download iStudy. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.
Module 2
CMOS TECHNOLOGY CMOS inverters, voltage transfer characteristics, propagation delay, power dissipation equation, MOSFET scaling and its impact on current and power equation MOS capacitance, MOS modelling, Spice Models Realization of digital circuits using CMOS technology: NAND Gate, NOR Gate, CMOS transmission gates, Multiplexer, 2:1, 4:1, XOR gate, XNOR gate, Complex logic circuits, AOI gate, OAI gate. 10
Module 3
CMOS SEQUENTIAL CIRCUITS 1-bit Latch, SR latch, gated SR latch, D-latch, positive triggered latch, negative triggered latch, master-slave register, flip flop, edge triggered register, JK flip flop, Latch vs Registers Timing Diagram: Timing definitions, setup time, hold time, clock to q delay, maximum clock frequency, mux based latch, CMOS Schmitt trigger, ring oscillator 10
Module 4
For complete syllabus and results, class timetable and more pls download iStudy. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.
Module 5
FINITE STATE MACHINES 10
Introduction, Mealy machine, Moore machines, sequence detector, examples of sequence detector of 4 bit sequence, representing counters using FSM diagrams
Course Outcomes:
After studying this course, students will be able to understand:
- Construction and working of MOSFETs
- CMOS technology and Realization of digital circuits using CMOS technology
- CMOS sequential circuits
- Registers and Counters
- Interpretation of performance characteristics of Mealy and Moore Models
Graduate Attributes (as per NBA):
- Engineering Knowledge.
- Problem Analysis.
- Design / development of solutions (partly).
- Interpretation of data.
Question paper pattern:
- The question paper will have ten questions.
- Each full Question consisting of 20 marks
- There will be 2 full questions (with a maximum of four sub questions) from each module.
- Each full question will have sub questions covering all the topics under a module.
- The students will have to answer 5 full questions, selecting one full question from each module.
Text Books:
- D. P. Kothari and J. S Dhillon, Digital Circuits and Design, Pearson, 2016, ISBN: 9789332543539.
Reference Books:
- Donald D. Givone, Digital Principles and Design, McGraw Hill.
- Charles H Roth, Jr., Fundamentals of logic design, Cengage Learning.
- David A. Bell, Electronic Devices and Circuits, Oxford University Press.
For detail syllabus of all other subjects of BE Nano, 2017 scheme do visit Nano 3rd Sem syllabus for 2017 scheme.
Dont forget to download iStudy for latest syllabus and results, class timetable and more.