Low Power Vlsi Design Med Elec 7th Sem Syllabus for VTU BE 2017 Scheme (Professional Elective-III)

Low Power Vlsi Design detail syllabus for Medical Electronics (Med Elec), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17ML743), and for exam duration, Teaching Hr/week, Practical Hr/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.

For all other med elec 7th sem syllabus for be 2017 scheme vtu you can visit Med Elec 7th Sem syllabus for BE 2017 Scheme VTU Subjects. For all other Professional Elective-III subjects do refer to Professional Elective-III. The detail syllabus for low power vlsi design is as follows.

Module 1

Needs for Low Power Chips, Charging and Discharging Capacitance, Short circuit Current of an Inverter, Short Circuit Current Variation with Output Load and Input Signal Slope, CMOS Leakage Current, Static Current, Basic Principles of Low Power design, Low Power Figure of Merits.(Text 1: Chapter 1) Sources of Dissipation in Digital Integrated Circuits, Degrees of Freedom, Recurring themes in Low Power, Emerging Low Power Approaches, Dynamic Dissipation in CMOS, Constraints on Vt Reduction, Impact of Technology Scaling, Technology and Device Innovation. (Text 2: 1.2, 1.3, 1.4, 1.5, 2.2, 2.4, 2.6, 2.7.

Module 2

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Module 3

Probabilistic Power Analysis: Random Logic Signals, Probability and Frequency, Probabilistic Power Analysis techniques, Signal Entropy. (Text 1: Chapter 3) Circuit: Transistor and Gate sizing, Equivalent Pin Ordering, Network Restructuring and Reorganization. (Text 1: 4.1, 4.2, 4.3.

Module 4

Logic: Gate Reorganization, Gate Signaling, Logic Encoding, State Machine Encoding, Pre computation Logic, Power Reduction in Clock Networks, CMOS Floating node. (Text 1: 5.1, 5.2, 5.3, 5.4, 5.5, 6.1, 6.2) Low Power Clock Distribution: Single Driver vs. Distributed Buffer, Zero Skew vs. Tolerable Skew, Derivation of Tolerable Skew, Two Level Clock distribution Scheme. (Text 3: 5.2, 5.4, 5.4.1, 5.4.2.

Module 5

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Course Outcomes:

After studying this course, students will be able to:

1. Explain the types of power dissipation in circuits and factors affecting them.
2. Employ the power reduction techniques possible at different levels of design.
3. Describe the role of simulation possible at various levels of design.
4. Analyze the need for low power VLSI circuits.
5. Evaluate the power dissipation in circuits and analyze its probability.

Question paper pattern:

• The question paper will have TEN questions.
• Each full question carry 16 marks.
• There will be TWO full questions (with maximum of THREE sub questions) from each module.
• Each full question will have questions covering all the topics under a module.
• The students will have to answer FIVE full questions, selecting ONE full question from each module.

Text Books:

1. Practical Low Power Digital VLSI Design, Gary K. Yeap, Spriger, 2002.
2. Low Power Design Methodologies, Jan M. Rabaey and Massoud Pedram, Kluwer Academic Publisher, 2002.
3. Low Power CMOS VLSI Circuit Design, Kaushik Ray, Sharat Prasad, Wiley, 2000,

Reference Books:

1. Low Power Digital CMOS Design, Chandrakasan A. and Brodersen R. Springer, 1995.
2. Advanced Low Power Digital Circuit Techniques, M.S Elrabaa, Abu-Khater and M.I.Elmasry, Springer, 1997.
3. Logic Synthesis for Low Power VLSI Designs, S. Iman and M.Pedram, Springer, 1998.

For detail syllabus of all other subjects of BE Med Elec, 2017 regulation do visit Med Elec 7th Sem syllabus for 2017 Regulation.

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