Hdl Lab ECE 5th Sem Syllabus for VTU BE 2017 Scheme

Hdl Lab detail syllabus for Electronics & Communication Engineering (Ece), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17ECL58), and for exam duration, Teaching Hr/week, Practical Hr/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.

For all other ece 5th sem syllabus for be 2017 scheme vtu you can visit ECE 5th Sem syllabus for BE 2017 Scheme VTU Subjects. The detail syllabus for hdl lab is as follows.

Course Objectives:

This course will enable students to:

• Familiarize with the CAD tool to write HDL programs.
• Understand simulation and synthesis of digital design.
• Program FPGAs/CPLDs to synthesize the digital designs.
• Interface hardware to programmable ICs through I/O ports.
• Choose either Verilog or VHDL for a given Abstraction level.

Note: Programming can be done using any compiler. Download the programs on a FPGA/CPLD boards such as Apex/Acex/Max/Spart.an/Sinfi or equivalent and performance testing may be done using 32 channel pattern generator and logic analyzer apart from verification by simulation with tools such as Altera/Modelsim or equivalent.

Laboratory Experiments:

For complete syllabus and results, class timetable and more pls download iStudy. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.

Part – A:

PROGRAMMING

1. Write Verilog code to realize all the logic gates
2. Write a Verilog program for the following combinational designs
1. 2 to 4 decoder
2. 8 to 3 (encoder without priority & with priority)
3. 8 to 1 multiplexer.
4. 4 bit binary to gray converter
5. Multiplexer, de-multiplexer, comparator.
3. Write a VHDL and Verilog code to describe the functions of a Full Adder using three modeling styles.
4. Write a Verilog code to model 32 bit ALU using the schematic diagram shown below

A (31:0. B(31:0)
Opcode (3:0)
Output
Enable

• ALU should use combinational logic to calculate an output based on the four bit op-code input.
• ALU should pass the result to the out bus when enable line in high, and tri-state the out bus when the enable line is low.
• ALU should decode the 4 bit op-code according to the example given below.

OPCODE ALU Operation

5. A+B
6. A-B
7. A Complement
8. A*B
9. A AND B
10. A OR B
11. A NAND B
12. A XOR B
13. Develop the Verilog code for the following flip-flops, SR, D, JK and T.
14. Design a 4 bit binary, BCD counters (Synchronous reset and Asynchronous reset) and any sequence counters, using Verilog code.

Part – B:

INTERFACING (at least four of the following must be covered using VHDL/Verilog)

1. Write HDL code to display messages on an alpha numeric LCD display.
2. Write HDL code to interface Hex key pad and display the key code on seven segment display.
3. Write HDL code to control speed, direction of DC and Stepper motor.
4. Write HDL code to accept Analog signal, Temperature sensor and display the data on LCD or Seven segment display.
5. Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp etc.,) using DAC – change the frequency.
6. Write HDL code to simulate Elevator operation.

Course Outcomes:

For complete syllabus and results, class timetable and more pls download iStudy. Its a light weight, easy to use, no images, no pdfs platform to make students life easier.

Conduct of Practical Examinations:

1. All practicals are to be included for practical examination.
2. Strictly follow the instructions as printed on the cover page of answer script for breakup of marks.
3. Change of experiment is allowed only once and Marks allotted to the procedure part to be made zero.

For detail syllabus of all other subjects of BE Ece, 2017 scheme do visit Ece 5th Sem syllabus for 2017 scheme.

Dont forget to download iStudy for latest syllabus and results, class timetable and more.