Dsp Algorithms and Architecture detail syllabus for Telecommunication Engineering (Telecom), 2017 scheme is taken from VTU official website and presented for VTU students. The course code (17EC751), and for exam duration, Teaching Hr/week, Practical Hr/week, Total Marks, internal marks, theory marks, duration and credits do visit complete sem subjects post given below.
For all other telecom 7th sem syllabus for be 2017 scheme vtu you can visit Telecom 7th Sem syllabus for BE 2017 Scheme VTU Subjects. For all other Professional Elective-4 subjects do refer to Professional Elective-4. The detail syllabus for dsp algorithms and architecture is as follows.
Course Objectives:
This course will enable students to:
- Figure out the knowledge and concepts of digital signal processing techniques.
- Understand the computational building blocks of DSP processors and its speed issues.
- Understand the various addressing modes, peripherals, interrupts and pipelining structure of TMS320C54xx processor.
- Learn how to interface the external devices to TMS320C54xx processor in various modes.
- Understand basic DSP algorithms with their implementation.
Module 1
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Module 2
Architectures for Programmable Digital Signal – Processing Devices: Introduction, Basic Architectural Features, DSP Computational Building Blocks, Bus Architecture and Memory, Data Addressing Capabilities, Address Generation Unit, Programmability and Program Execution, Speed Issues, Features for External Interfacing.
Module 3
Programmable Digital Signal Processors: Introduction, Commercial Digital Signal-processing Devices, Data Addressing Modes of TMS32OC54XX, Memory Space of TMS32OC54xx Processors, Program Control. Detail Study of TMS320C54X & 54xx Instructions and Programming, On – Chip Peripherals, Interrupts of TMS32OC54XX Processors, Pipeline Operation of TMS32OC54xx Processor.
Module 4
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Module 5
Interfacing Memory and Parallel I/O Peripherals to Programmable DSP Devices: Introduction, Memory Space Organization, External Bus Interfacing Signals. Memory Interface, Parallel I/O Interface, Programmed I/O, Interrupts and I/O Direct Memory Access (DMA).
Interfacing and Applications of DSP Processors:
Introduction, Synchronous Serial Interface, A CODEC Interface Circuit, DSP Based Bio-telemetry Receiver, A Speech Processing System, An Image Processing System.
Course Outcomes:
At the end of this course, students would be able to
- Comprehend the knowledge and concepts of digital signal processing techniques.
- Apply the knowledge of DSP computational building blocks to achieve speed in DSP architecture or processor.
- Apply knowledge of various types of addressing modes, interrupts, peripherals and pipelining structure of TMS320C54xx processor.
- Develop basic DSP algorithms using DSP processors.
- Discuss about synchronous serial interface and multichannel buffered serial port (McBSP) of DSP device.
- Demonstrate the programming of CODEC interfacing.
Text Books:
Digital Signal Processing, Avatar Singh and S. Srinivasan, Thomson Learning, 2004.
Reference Books:
- Digital Signal Processing: A practical approach, Ifeachor E. C., Jervis B. W Pearson-Education, PHI, 2002.
- Digital Signal Processors, B Venkataramani and M Bhaskar, TMH, 2nd, 2010
- Architectures for Digital Signal Processing, Peter Pirsch John Weily, 2008
For detail syllabus of all other subjects of BE Telecom, 2017 regulation do visit Telecom 7th Sem syllabus for 2017 Regulation.
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